CPU Core Partitioning for RAN Baseband Workload Idle State Coordination

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Solution Overview

Problem

In radio access networks (RAN), the allocation of tasks to hyperthreads (HTs) is often random and unaware of idle state requirements, leading to inefficient utilization and power consumption issues due to unpredictable transitions into idle states.

Innovation Solution

A method and system for optimizing CPU resource allocation by allocating specific cores and HTs to perform specific types of tasks, allowing coordinated task completion and transitioning to idle states based on task completion, thereby reducing power consumption and improving resource efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If tasks are allocated randomly to hyperthreads without considering idle state requirements, then task allocation simplicity is improved, but CPU utilization efficiency deteriorates due to unpredictable idle state transitions

Engineering Contradiction:
Improvetask allocation simplicityVSAvoidCPU utilization efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent segments CPU cores into different types (first type cores and second type cores) with distinct functionalities. First type cores are dedicated to handling wake-up scenarios and transitions, while second type cores handle normal task execution. This segmentation allows the system to optimize idle state transitions by directing specific task types to appropriate core types, thereby improving CPU utilization efficiency without complicating the overall task allocation mechanism.

Inventive Principle:
Principle #1Segmentation

2Loss of energy

If hyperthreads enter idle state randomly without coordinated task completion, then power consumption is reduced during idle periods, but overall system performance deteriorates due to non-optimal idle state timing

Engineering Contradiction:
Improvepower consumption during idle periodsVSAvoidsystem performance
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The patent implements a feedback mechanism where the system monitors task completion status across hyperthreads and uses this information to coordinate idle state transitions. When tasks are completed and hyperthreads become idle, the system receives feedback about the idle status and coordinates transitions to idle states optimally. This feedback-driven approach ensures that idle states are entered at optimal times, balancing power consumption reduction with maintained system performance.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If multiple task types are distributed across all cores without specialization, then core versatility is improved, but idle state coordination deteriorates making it difficult to transition cores to idle states efficiently

Engineering Contradiction:
Improvecore versatilityVSAvoididle state transition efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies local quality by assigning different functional characteristics to different core types. First type cores are specialized for handling wake-up scenarios and managing transitions from idle states, while second type cores are optimized for normal task execution. This localized functional differentiation enables efficient idle state coordination within each core type while maintaining overall system versatility through the combination of specialized cores.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240160485A1System and method for radio access network baseband workload partitioning
Publication Date: 2024.05.16 RAKUTEN SYMPHONY INC
  • US20240160485A1 patent drawing
  • US20240160485A1 patent drawing
  • US20240160485A1 patent drawing

AI summary

An apparatus for resource allocation of a central processing unit (CPU) including a plurality of cores includes at least one memory storing instructions, and at least one processor configured to execute the instructions to allocate a first core of the plurality of cores of the CPU to perform tasks of a first type, allocate a second core of the plurality of cores of the CPU to perform tasks of a second type that is different from the first type, assign at least one task of the first type to be performed by the first core, and transition the first core to an idle state based on the at least one task of the first type being completed.