CPU Core Scan Test Circuit for Multi-Core Systems
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Solution Overview
Problem
Existing semiconductor diagnostic test methods for CPU cores in multi-core architectures face challenges in minimizing performance deterioration during fault diagnosis, as they often require all CPU boards to be non-operational, leading to decreased operational performance and lack specific methods to prevent or minimize this deterioration.
Innovation Solution
A semiconductor device that performs periodic scan tests on each CPU core in a predetermined order, ensuring execution time periods do not overlap, allowing for immediate fault detection while maintaining high operation performance by isolating the affected core during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a boundary scan test is performed by using a scan chain extending through all CPU boards, then fault diagnosis coverage is improved, but operation performance deteriorates because all CPU boards become non-operational during testing
Solution Approach 1:
The patent divides the single long scan chain into multiple separate scan chains, with each CPU board having its own independent scan chain. This segmentation allows individual boards to be tested without affecting the operational status of other boards, thereby maintaining system productivity while achieving comprehensive fault diagnosis coverage.
Solution Approach 2:
The patent implements periodic scan tests where each CPU board is tested at different time intervals. By scheduling tests periodically and sequentially for each board rather than simultaneously, the system maintains high operation performance while ensuring thorough fault diagnosis of all CPU boards.
2Reliability
If a self-diagnosis program is created to achieve high diagnosis coverage, then fault detection rate is improved, but execution time becomes considerably long
Solution Approach 1:
The patent replaces software-based self-diagnosis programs with hardware-based scan tests. This substitution eliminates the need for lengthy program execution by using dedicated hardware circuits to perform fault detection, thereby achieving high fault detection rates without the time penalty associated with software execution.
Solution Approach 2:
The patent performs fault diagnosis during idle periods or between operational tasks by utilizing unused time slots for scan tests. This preliminary action approach ensures that fault detection is completed without interfering with the main operational workflow, minimizing time loss while maintaining high detection rates.
3Reliability
If scan tests are performed on multiple CPU boards, then comprehensive fault diagnosis is achieved, but all boards must be non-operational leading to performance deterioration
Solution Approach 1:
The patent segments the testing architecture so that each CPU board has its own independent scan chain and testing resources. This allows comprehensive fault diagnosis of all boards to be performed sequentially without requiring all boards to be non-operational simultaneously, thereby maintaining system productivity.
Solution Approach 2:
The patent ensures continuous useful action by maintaining the operational status of non-tested CPU boards while performing scan tests on selected boards. This continuity allows the system to achieve comprehensive fault diagnosis while minimizing disruption to overall system performance and functionality.
Data Source
AI summary
A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.