Debugging Circuit for Multi-Core CPU Trace Data Sorting
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Solution Overview
Problem
Debugging multi-core systems with tightly coupled CPUs is challenging due to difficulties in tracking instruction execution and memory access events, especially in systems with pipelining processes, where concurrent events and rare malfunctions make it hard to ensure memory coherency and synchronization, and existing techniques fail to handle timing changes and pipelining operations effectively.
Innovation Solution
An information processing device with a debugging circuit that includes a trace acquisition circuit and a sorting logic unit to accurately collect and sort instruction execution analysis data and memory access data from CPUs, using separate FIFOs for each type of data and tagging them with time stamps to maintain proper sequencing, even in pipelining scenarios, allowing for effective debugging of multiple CPUs simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipelining processes are used to improve CPU performance, then instruction execution speed is improved, but tracking instruction execution order and memory access timing becomes difficult
Solution Approach 1:
The patent applies preliminary action by inserting trace instructions at predetermined locations in the instruction sequence before the actual execution occurs. These trace instructions mark specific points in the pipeline where trace data should be captured, ensuring that even with pipelining, the execution order and timing information can be accurately tracked without affecting the actual instruction execution performance.
2Productivity
If concurrent executions of multiple instructions are implemented to enhance performance, then processing throughput is improved, but debugging analysis becomes difficult
Solution Approach 1:
The patent applies local quality by implementing trace data collection at specific localized points within the concurrent execution flow. Instead of attempting to track all instructions globally, the system places trace instructions at predetermined locations where specific events occur, allowing accurate tracking of individual instruction execution order and memory access timing even when multiple instructions execute concurrently.
3Productivity
If multi-core systems with tightly coupled CPUs are used to improve performance, then processing capability is improved, but synchronization and memory coherency tracking becomes difficult
Solution Approach 1:
The patent applies preliminary action by placing trace instructions at predetermined synchronization points and memory access locations before the actual operations occur. This allows the system to capture timing and ordering information about inter-CPU synchronization events and memory coherency operations, making it possible to verify synchronization correctness and memory access ordering in multi-core systems without affecting their performance.
4Measurement precision
If trace data collection is added to track instruction execution, then debugging accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing trace instructions that serve multiple functions: they mark predetermined locations for trace data collection, provide timing information, and indicate the type of event being traced. This multi-functionality reduces the need for separate dedicated hardware components for each tracing function, thereby improving debugging accuracy while minimizing the increase in device complexity.
Data Source
AI summary
The invented device includes a central processing unit(s), each CPU including an execution unit coupled to an operand bus and a control unit that controls operation of the execution unit, based on fetched instructions, and a debugging circuit that obtains trace data about how a program is executed in each CPU. The control unit includes a debugging function unit that collects instruction execution analysis data in the CPU. The debugging circuit includes a trace acquisition circuit(s) that imports instruction execution analysis data collected by the debugging function unit and data received from the operand bus via logic circuits used for separate purposes and a trace output circuit(s) for delivering outside the output of the trace acquisition circuit. In the trace acquisition circuit, a sorting logic unit is provided that sorts instruction execution analysis data collected by the debugging function unit and data received from the operand bus.