Dual-Core CPU Dedicated Instruction Code Transfer
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Solution Overview
Problem
There is a need for an improved instruction set in multi-core microcontrollers with digital signal processing capabilities, particularly for dual-core devices, to enable efficient communication and code protection between processor cores, while minimizing silicon usage and optimizing performance for applications like SMPS.
Innovation Solution
The introduction of dedicated instructions, such as LDSLV and VFSLV, which allow for the transfer and verification of program instructions between the master and slave processing cores, utilizing a communication interface that supports auto-increment addressing and error correction, along with a code protection scheme that defines security levels for different memory segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated instructions are added to enable efficient code transfer and verification between cores, then productivity and reliability are improved, but device complexity increases
Solution Approach 1:
The patent segments the code transfer and verification process into distinct dedicated instructions (LDSLV for loading, VFSLV for verification). Each instruction handles a specific aspect of the inter-core code transfer process, improving efficiency through specialized handling while keeping each instruction's function well-defined and manageable.
Solution Approach 2:
The patent introduces a buffer as an intermediary component between the master core and slave core memory systems. The buffer facilitates efficient data transfer by allowing the master core to write code words that are then automatically transferred to the slave core, reducing direct communication overhead and improving transfer productivity.
2Reliability
If code protection schemes are implemented across multiple memory segments, then reliability and security are improved, but device complexity increases
Solution Approach 1:
The patent divides the program memory into multiple segments (boot segment, general segment, test segment) with independent protection settings. Each segment can have its own security level and protection characteristics, allowing flexible and robust code protection while managing complexity through clear segmentation and standardized protection mechanisms for each segment.
Solution Approach 2:
Different memory segments can have different protection qualities and security levels. The boot segment, general segment, and test segment can each be configured with appropriate protection settings based on their specific requirements, allowing tailored security measures for different code regions rather than a one-size-fits-all approach.
3Productivity
If auto-increment addressing is implemented in dedicated instructions, then productivity is improved, but device complexity increases
Solution Approach 1:
The dedicated instructions incorporate auto-increment addressing that automatically updates address pointers during execution. This preliminary automation of address management eliminates the need for manual address updating in loops, significantly improving data transfer productivity when moving code words between memory segments while keeping the addressing mechanism integrated into the instruction execution flow.
Data Source
Figure 1~1A
Figure 1B
Figure 2
AI summary
An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.