CPU Die Power Management via CLKREQ Messaging Protocol

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Solution Overview

Problem

The integration of a PCIe root port on a CPU die limits the ability of the CPU to enter various idle states due to the lack of 3.3V GPIO pins and the reference clock supply being located at the Platform Controller Hub, preventing effective power management features like L1 sub-state and Dynamic Hot Plug Power Management.

Innovation Solution

The implementation of the CLKREQ Messaging Protocol allows for autonomous power management by establishing a communication channel between the CPU and the Platform Controller Hub to control and handshaking CLKREQ# GPIO pin control, enabling deeper idle states and sleep states with reference clock gating.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If PCIe root port is integrated on CPU die, then device integration and compactness are improved, but power management capability deteriorates due to lack of 3.3V GPIO pins and reference clock supply control

Engineering Contradiction:

ImproveCPU die integrationVSAvoidpower management capability

Core Design Contradiction:

Area of moving objectVSAdaptability or versatility

Solution Approach 1:

The patent introduces a messaging protocol as an intermediary communication mechanism between the CPU root port controller and the platform controller hub. This protocol enables the CPU to request clock signals and negotiate power management states without direct hardware GPIO pins, effectively mediating the power control function through software/firmware communication layers.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The messaging protocol serves multiple functions: it enables clock request signaling, facilitates power state negotiation, supports idle state transitions, and provides a universal communication interface for various power management scenarios. This multi-functional approach replaces the need for dedicated hardware pins while maintaining comprehensive power management capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If reference clock supply is located at Platform Controller Hub, then system architecture flexibility is improved, but CPU idle state entry is hindered due to inability to control clock gating

Engineering Contradiction:

Improvesystem architecture flexibilityVSAvoidCPU idle state power consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The messaging protocol implements a feedback mechanism where the CPU can send clock request messages to the platform controller hub and receive acknowledgments. This feedback loop enables the CPU to dynamically control clock supply based on its idle state requirements, allowing effective power management despite the clock source being external to the CPU.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The protocol allows the CPU to preliminarily request clock signals before actually needing them for operation. By sending clock request messages in advance when transitioning to idle states, the CPU can ensure timely clock gating and maximize power savings without compromising system responsiveness.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If multiple high-speed Serial I/O ports are provided, then I/O capability is improved, but idle power consumption increases due to more components requiring power management

Engineering Contradiction:

ImproveI/O capabilityVSAvoididle power consumption

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The messaging protocol enables independent power management for each PCIe root port and connected device. Instead of managing all I/O ports as a single unit, the system can segment power control at the individual port level, allowing ports not in use to enter low-power states while maintaining I/O capability when needed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The protocol provides dynamic power management where each I/O port can independently transition between active and idle states based on actual usage requirements. This dynamic control allows the system to optimize power consumption in real-time while maintaining high I/O capability when ports are actively used.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11016549B2Method, apparatus, and system for power management on a CPU die via clock request messaging protocol

Publication Date: 2021.05.25 INTEL CORP

AI summary

Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.