CPU Architecture With DMA ROM To RAM Transfer
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Solution Overview
Problem
Existing computing systems face challenges in achieving fast start-up and recovery times, particularly in critical applications like autonomous vehicles and guidance systems, where brief losses of processing power can lead to inaccurate navigation and communication disruptions, and current methods like sleep or hibernation modes are inadequate due to slower non-volatile storage and added complexity from redundant processing.
Innovation Solution
A central processing unit (CPU) architecture that employs a direct memory access (DMA) engine to transfer ROM-resident software instructions to RAM upon power-up, with a memory management unit dynamically updating address translations, allowing the CPU to execute instructions from RAM once available, while still executing ROM-based instructions until the RAM is fully transferred, thus leveraging RAM's faster access speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the system uses non-volatile memory (ROM) for storing software instructions, then the system maintains data without power and achieves fast start-up response, but the execution speed is limited compared to volatile memory (RAM)
Solution Approach 1:
The patent applies preliminary action by pre-transferring the system image from ROM to RAM during the boot process. The DMA engine automatically copies the operating system and application software from ROM to RAM before the CPU needs to execute them at full speed, so that when execution begins, the data is already in the faster RAM memory.
Solution Approach 2:
The patent uses a DMA (Direct Memory Access) engine as an intermediary between ROM and RAM. This intermediary component handles the data transfer automatically without requiring CPU intervention, enabling efficient movement of the system image from slow ROM to fast RAM while the CPU continues initialization tasks.
2Use of energy by moving object
If the system enters sleep or hibernation mode to conserve power, then energy consumption is reduced, but the start-up response time increases due to non-volatile storage access
Solution Approach 1:
The system maintains the system image in ROM (which retains data without power) and prepares the RAM memory structure in advance. Upon wake-up from sleep or hibernation, the DMA engine can quickly transfer the image to RAM without requiring full system re-initialization, achieving fast recovery while maintaining low power consumption during idle states.
3Reliability
If redundant processing architecture is used to support high availability, then system reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service through automatic failover mechanisms where the system can autonomously switch between primary and backup processing units. The DMA engine and memory management unit automatically redirect operations to redundant components without requiring complex external control or manual intervention, maintaining high availability while minimizing added complexity.
Data Source
AI summary
Aspects are directed to a start-up or recovery method and a central processing unit (CPU) architecture. In one example, the CPU architecture includes read-only memory (ROM) storing instructions addressable by a first range of physical memory addresses, random access memory (RAM), a direct memory access (DMA) engine, the DMA engine controllable to transfer the instructions from the ROM to RAM, the instructions addressable by a second range of physical memory addresses at the RAM, a memory management unit configured to translate a range of virtual addresses to the first range while in ROM, and translate the range of virtual memory addresses to the second range while in RAM, and a CPU to execute a DMA interrupt service routine to update the memory management unit to translate the range of virtual addresses to the second range of physical memory addresses while the DMA engine transfers the instructions to RAM.