CPU-DRAM Interconnect Testing Using Adjustable Driver Resistance
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Solution Overview
Problem
Current board level testing techniques are inadequate for ensuring the electrical integrity of platform components without requiring a full system reset, particularly due to limitations in testing DDR memory, which is a significant portion of modern board connectivity, and are not scalable with increasing DDR speeds and varying DRAM protocols.
Innovation Solution
A method for testing platform connectivity between a CPU and DRAM that uses adjustable pull-up and pull-down resistances, a comparator, and analog-to-digital conversion to set and verify voltage levels independently of DDR speeds, allowing for protocol-independent testing of signal paths and detection of faults like opens and shorts, and bypasses the need for a complete system reset by using an external clock during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full system reset is performed to test board electrical integrity, then the testing can be completed, but the time-to-market is extended and design convergence effort increases
Solution Approach 1:
The patent applies preliminary action by performing board electrical integrity testing during the reset process itself, rather than requiring a separate post-reset testing phase. The testing is integrated into the reset sequence, allowing defects to be detected before the system fully operationalizes, thus eliminating the need to extend time-to-market for additional testing cycles.
Solution Approach 2:
The patent merges the board testing function with the reset process by integrating testing logic into the reset controller. The reset controller simultaneously manages the reset sequencing and performs electrical integrity measurements on board components, combining two previously separate functions into a unified process that reduces overall testing time.
2Adaptability or versatility
If DDR memory testing is performed using CPU functional traffic at low speeds, then testing can be conducted, but the testing is not suitable for high-speed DDR protocols and variants
Solution Approach 1:
The patent introduces an intermediary testing controller that mediates between the CPU and DRAM for electrical integrity testing. This dedicated testing controller implements protocol-agnostic measurement logic that can characterize signal integrity without requiring actual DDR protocol compliance, allowing accurate testing across different DDR generations and variants without being constrained by protocol-specific requirements.
Solution Approach 2:
The patent extracts the electrical integrity measurement function from the CPU and places it in a dedicated testing controller. This separation allows the testing logic to be independent of CPU functional requirements and DDR protocol implementations, enabling universal testing capability across different memory types and protocols while maintaining testing accuracy through specialized measurement circuits.
3Ease of operation
If DRAM logic incorporates typical board testing logic, then testing capability is provided, but additional pins (4 TAP pins) and cost are required
Solution Approach 1:
The patent makes the reset controller multi-functional by giving it both reset sequencing responsibilities and board electrical integrity testing capabilities. This universal controller uses existing reset infrastructure and pins to perform testing functions, eliminating the need for dedicated test pins while maintaining comprehensive board testing capability across different board configurations.
Solution Approach 2:
The patent implements self-service by having the reset controller perform electrical integrity measurements on board components using its own internal resources and existing pin infrastructure. The testing logic leverages the reset controller's inherent ability to drive and sense signals on board traces, allowing the system to test itself without requiring external testing equipment or additional dedicated test pins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable, scalable, and protocol-independent testing of board connections, reducing design effort and time-to-market pressures by allowing testing without a full system reset and ensuring the electrical integrity of platform boards across different DDR generations and vendor implementations.
Implementation Method 1
a comparator having a first input coupled to the driver output and a second input coupled to a voltage reference, the comparator being operable to generate a comparator output in response to comparing the driver voltage with the voltage reference
Implementation Method 2
a driver with adjustable pullup and pulldown resistances and having a driver output to output a driver voltage during test mode
Data Source
AI summary
A method and apparatus for platform component interconnect testing is disclosed. In one embodiment, an integrated circuit comprises: a plurality of interface circuitries, wherein each interface circuitry comprises a driver with adjustable pullup and pulldown resistances and having a driver output to output a driver voltage to a pad during test mode, and a comparator having a first input coupled to the driver output and a second input coupled to a voltage reference, the comparator being operable to generate a comparator output in response to comparing the driver voltage with the voltage reference; and analysis circuitry coupled to receive the comparator output, the analysis circuitry operable, during the test mode, to detect existence of a fault associated with a signal path coupled to the pad for each interface circuitry.