CPU-FPGA Heterogeneous Architecture for CNN Acceleration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Convolutional neural networks (CNNs) are memory-intensive and require specialized hardware for efficient implementation, but such hardware is limited in flexibility and often struggles with complex operations.
Innovation Solution
A deep processing unit (DPU) is designed, combining a general CPU with a special neural network processing unit, utilizing a programmable logic module and direct memory access (DMA) for efficient data and instruction transmission, and incorporating a computing complex with processing elements for convolutional operations, adder trees, and non-linear modules to enhance flexibility and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If special designed hardware is used for CNN implementation, then computation speed is improved, but flexibility deteriorates
Solution Approach 1:
The system is divided into two distinct parts: a CPU for control and flexibility, and a programmable logic module for accelerated computation. This segmentation allows each component to specialize in its strengths while working together as a unified system, resolving the contradiction between speed and flexibility.
Solution Approach 2:
The programmable logic module can be dynamically reconfigured through FPGA technology, allowing the hardware architecture to adapt to different CNN models and operations. This dynamic reconfigurability provides both the speed of specialized hardware and the flexibility to handle various computational tasks.
2Adaptability or versatility
If CPU is used for CNN processing, then flexibility is maintained, but computation speed deteriorates
Solution Approach 1:
The system merges the CPU's flexibility with the programmable logic module's computational power through a unified architecture. The CPU handles control flow and memory management while the programmable logic module performs intensive computations, achieving both flexibility and high speed simultaneously.
Solution Approach 2:
A buffer and DMA controller serve as intermediaries between the CPU and programmable logic module, enabling efficient data transfer and coordination. This intermediary layer allows the CPU to maintain flexibility while the programmable logic module achieves high-speed processing without direct CPU intervention for every operation.
3Measurement precision
If memory-intensive operations are performed, then CNN accuracy is maintained, but memory access time deteriorates
Solution Approach 1:
Data is pre-loaded into on-chip buffers before processing begins. This preliminary action reduces the need for frequent external memory accesses during computation, maintaining accuracy by keeping necessary data readily available while significantly reducing memory access time delays.
Solution Approach 2:
The system maintains continuous data flow between external memory, buffers, and processing elements through DMA controllers. This continuity ensures that memory-intensive operations can proceed without interruption, maintaining CNN accuracy while minimizing idle time and optimizing memory access efficiency.
Data Source
AI summary
The present invention relates to artificial neural network (ANN), for example, convolutional neural network (CNN). In particular, the present invention relates to how to implement and optimize a convolutional neural network based on an embedded FPGA. Specifically, it proposes a CPU+FPGA heterogeneous architecture to accelerate ANNs.