CPU Interconnect Fault Tolerance via FPGA Switch Module
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Solution Overview
Problem
Current CPU interconnection solutions suffer from poor expansibility, high costs, and low system performance due to limited interconnection interfaces and increased data transmission delays, with a lack of fault tolerance in case of link errors.
Innovation Solution
A method and system utilizing Field Programmable Gate Arrays (FPGAs) with Quick Path Interconnect (QPI) and Serial Deserial (SerDes) interfaces to establish multiple data channels for interconnection between CPUs, enabling monitoring and recovery of faulty links, thereby enhancing fault tolerance and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If full direct connection manner is used between CPUs, then interconnection speed is improved, but device complexity and cost increase due to multiple high-speed interfaces required
Solution Approach 1:
The patent introduces a switch module as an intermediary device between CPUs. Instead of requiring each CPU to have multiple high-speed direct connection interfaces, the switch module mediates interconnection by receiving data from one CPU and forwarding it to another CPU, thereby reducing the complexity of direct interconnection while maintaining high-speed data transfer capability
2Adaptability or versatility
If switch module is employed for CPU interconnection, then expansibility is improved, but data transmission delay increases due to jump point judgment
Solution Approach 1:
The patent applies preliminary action by pre-establishing routing paths and performing jump point judgment in advance. The switch module pre-calculates and stores optimal routing information, so that during actual data transmission, no real-time jump point judgment is needed, thereby reducing data transmission delay while maintaining expansibility
3Adaptability or versatility
If multiple chips are added for NC node control and switch module, then interconnection functionality is improved, but system cost increases
Solution Approach 1:
The patent merges the NC node control function and switch module function into a single integrated chip. Instead of using separate chips for each function, the integrated design combines both functionalities, reducing the total number of chips required and thereby lowering system cost while maintaining full interconnection functionality
4Device complexity
If limited number of interconnection interfaces is used, then device complexity is reduced, but expansibility of CPU system deteriorates
Solution Approach 1:
The patent applies universality by designing the switch module with multi-functional capabilities. The switch module can dynamically configure connection paths to support various CPU interconnection topologies and scaling scenarios, allowing the system to expand without requiring additional specialized interfaces on each CPU, thereby maintaining low device complexity while improving expansibility
Data Source
AI summary
A system for implementing interconnection fault tolerance between CPUs, a first CPU and a second CPU implements interconnection through a first CPU interconnect device and a second CPU interconnect device. The system adds a data channel between a first SerDes interface of the first CPU interconnect device and a second SerDes interface of the second CPU interconnect device, and transmits link connection state information and a link control signal through the added data channel. The system monitors a link state of any one link in a CPU interconnection system, transmits the link state through the added data channel, recovers any one of the connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.