Synchronized CPU-FPGA Simulation With Multi-Rate Time Master
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Solution Overview
Problem
Current SIL simulations cannot effectively incorporate FPGA components due to significant speed disparities and asynchronous execution, making high-performance simulations of electric motors and power electronics impractical.
Innovation Solution
A method for synchronized SIL simulation is developed, where simulation components are assigned different step sizes and executed on computing and accelerator farms, with a time master triggering synchronized execution steps to align with real-time HIL simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FPGA components are incorporated into SIL simulations to achieve high-performance simulation of electric motors and power electronics, then simulation speed and performance are improved, but execution synchronization and integration with processor-based components become problematic due to significant speed disparities
Solution Approach 1:
The simulation model is divided into multiple components with different step sizes - a first simulation component executed on a processor with a first step size, and a second simulation component executed on an FPGA with a second step size. This segmentation allows each component to operate at its optimal speed while maintaining overall system functionality.
Solution Approach 2:
A time master component acts as an intermediary between the processor-based first simulation component and the FPGA-based second simulation component. The time master triggers execution of both components and manages their synchronization, enabling coordinated operation despite their different execution speeds and architectures.
2Productivity
If different simulation step sizes are assigned to processor and FPGA components to optimize their respective performance, then calculation efficiency is improved, but coordinating execution and maintaining time synchronization become more complex
Solution Approach 1:
The system dynamically adapts to different step sizes by allowing the first simulation component to execute with a first step size and the second simulation component to execute with a second step size. The time master dynamically triggers execution based on the relationship between these step sizes, enabling efficient calculation while managing coordination complexity.
3Adaptability or versatility
If event-based or virtual time domain execution is used in SIL simulation to allow flexible calculation timing, then adaptability to different simulation scenarios is improved, but coupling with real FPGA hardware for acceleration becomes difficult
Solution Approach 1:
The system changes the time domain parameter from purely virtual/event-based to a hybrid approach where a time master triggers execution based on defined step sizes. This parameter change enables the FPGA component to operate in real-time while maintaining compatibility with the virtual time domain processor simulation, bridging the gap between software flexibility and hardware performance.
Data Source
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Figure 3
AI summary
Method for the synchronized simulation of a first simulation component by means of a CPU, and a second simulation component by means of an FPGA, wherein the second component is assigned a shorter simulation step size than the first component, comprising the steps of: loading the first simulation component onto a computing farm with computer components and the second simulation component onto an accelerator farm with accelerator components, defining a time master that triggers an execution of the two simulation components, wherein a trigger initiates the execution of a simulation step comprising a time step of the first simulation component and a plurality n of time steps of the second simulation component, carrying out the simulation by repeatedly triggering a simulation step, wherein a new simulation step is triggered,as soon as the first and second simulation components have completed the calculations of the current simulation step. Furthermore, the invention relates to a computer system and a non-volatile data storage device.