CPU Heatsink Power Delivery Stack-Up for High-Current Packaging

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Solution Overview

Problem

As CPUs require higher supply currents at lower operating voltages and have increasing pin counts for power delivery, existing technologies face challenges in efficiently routing and delivering power and ground signals, leading to increased complexity and heat generation in CPU packages.

Innovation Solution

The proposed solution involves a processor mounting stack-up that includes a heat sink, insulating collar, power delivery hat, conductive stack gasket, CPU, and printed circuit board (PCB), where the CPU's ground and power contacts are routed through a substrate to dedicated pads on the CPU, and then connected to the PCB via the stack-up components, ensuring efficient power and ground delivery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the CPU pin count increases to meet higher power delivery requirements, then the power delivery capability is improved, but the device complexity increases

Engineering Contradiction:
Improvepower delivery capabilityVSAvoidCPU package complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent segments the CPU package into distinct functional layers: the CPU die with its substrate, a separate heatsink assembly with integrated power delivery components, and a motherboard interface. This segmentation allows the power delivery function to be handled by dedicated components (power delivery hat, conductive gasket) rather than increasing CPU pin count, thus improving power capability without proportionally increasing overall package complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The heatsink assembly is designed to serve multiple functions simultaneously: thermal management through heat dissipation, power delivery through the conductive gasket and power delivery hat, and mechanical support for the CPU. This multi-functionality reduces the need for separate dedicated power delivery components, thereby improving power delivery capability without linearly increasing device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Power

If more power contacts are routed to the CPU substrate, then the power delivery capability is improved, but the heat generation increases

Engineering Contradiction:
Improvepower delivery capabilityVSAvoidheat generation
Core Design Contradiction:
PowerVSTemperature

Solution Approach 1:

The patent introduces an intermediary power delivery path through the conductive gasket and power delivery hat that connects the motherboard power sources directly to the CPU substrate. This intermediary pathway distributes power closer to the CPU die, reducing current flow through long substrate traces and thereby minimizing I²R heating while maintaining high power delivery capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent transitions from planar power delivery through substrate traces to a three-dimensional power distribution architecture using stacked layers (conductive gasket, power delivery hat, substrate). This vertical dimensionality allows power to be delivered through multiple parallel pathways and closer to the heat source, reducing resistive heating while maintaining high power capability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12213252B2CPU for heatsink based power delivery
Publication Date: 2025.01.28 DELL PROD LP
  • US12213252B2 patent drawing
  • US12213252B2 patent drawing
  • US12213252B2 patent drawing

AI summary

A CPU includes a processor die and a substrate. The processor die includes first signal contacts, power contacts, and ground contacts. The processor die is affixed and electrically coupled to the substrate on a first surface of the substrate. The substrate routes the first signal contacts to associated second signal contacts on a second surface of the substrate. The substrate further routes a subset of the power contacts to a power pad on the first surface of the substrate, and routes a subset of the ground contacts to a ground pad on the first surface of the substrate.