CPU Hot-Swapping via Dual PCH and DMI Switch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing computing systems face challenges in hot-swapping the 'legacy socket' CPU0, as it requires a system reset, which is unacceptable in mission-critical systems, and the CPU on-lining flow is unacceptably slow due to sequential memory training processes.
Innovation Solution
A system utilizing a dual platform controller hub (PCH) and direct media interface (DMI) switch, implemented using a discrete field-programmable gate array (FPGA), allows for efficient memory training and enables CPU0 hot-swapping without a reset by switching DMI and legacy resources between good and bad CPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If CPU0 hot-swapping is implemented using traditional methods, then CPU replacement is possible, but system reset is required which causes downtime
Solution Approach 1:
The system is segmented into multiple PCH instances (first and second PCH) that can independently manage different CPU sockets. This segmentation allows one CPU to be replaced while the other continues to operate, enabling hot-swapping without system reset and maintaining system availability.
Solution Approach 2:
The system dynamically switches between different PCH-CPU configurations. When CPU0 needs to be hot-swapped, the system transitions from using the first PCH to using the second PCH, allowing seamless CPU replacement without system downtime. This dynamic switching capability resolves the contradiction between ease of operation and system reliability.
2Reliability
If sequential memory training is used during CPU on-lining, then memory initialization is completed, but the process is unacceptably slow
Solution Approach 1:
Memory training is segmented and distributed across multiple PCH instances. Instead of sequentially training all memory through one PCH, the system divides memory training tasks across multiple PCH, allowing parallel processing and significantly reducing the overall time required for CPU on-lining while ensuring complete memory initialization.
Solution Approach 2:
The second PCH is pre-configured and ready to take over memory training responsibilities before CPU0 is actually replaced. This preliminary preparation allows the system to switch to the pre-configured second PCH immediately upon CPU replacement, eliminating the need for slow sequential memory training and accelerating the CPU on-lining process.
3Reliability
If dual PCH and DMI switch architecture is implemented, then CPU hot-swapping without reset is enabled, but device complexity increases
Solution Approach 1:
Both PCH instances are configured with identical functionality and capabilities, allowing either PCH to serve any CPU socket. This universal design simplifies the overall system architecture by eliminating the need for complex, asymmetric configurations while enabling seamless hot-swapping. The symmetry and interchangeability of PCH instances reduce configuration complexity compared to asymmetric designs.
Data Source
AI summary
There is disclosed in one example a multi-core computing system configured to provide a hot-swappable CPU0, including: a first CPU in a first CPU socket and a second CPU in a second CPU socket; a switch including a first media interface to the first CPU socket and a second media interface to the second CPU socket; and one or more mediums including non-transitory instructions to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N≠0.