CPU Interconnect Device Using QPI and SerDes Interfaces
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Solution Overview
Problem
Existing CPU interconnect systems suffer from poor scalability, long data transmission delays, and high costs due to limited interconnect interfaces and complex architectures.
Innovation Solution
A CPU interconnect device utilizing a Quick Path Interconnect (QPI) interface and Serializer-Deserializer (SerDes) interface to convert serial QPI data into parallel data and high-speed serial data, enabling efficient interconnection between CPUs with reduced data transmission delay and increased scalability by allowing flexible configuration of CPU connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Power CPUs with integrated NC controller are used for full direct-connection interconnection, then interconnection capability is achieved, but cost increases and scalability is limited
Solution Approach 1:
The system is divided into independent functional modules: CPU nodes with QPI interfaces and separate interconnect devices with SerDes interfaces. Each node can be independently configured and scaled, allowing flexible system composition without requiring integrated NC controllers in each CPU.
Solution Approach 2:
The interconnect device serves multiple functions: it provides serial communication capability, implements data routing between CPUs, and enables both direct and indirect connection topologies. This multi-functional design replaces the need for specialized NC controllers, reducing CPU complexity while maintaining interconnection capability.
2Ease of operation
If switch module with jump-point judgment is used for data exchange among NCs, then data routing is achieved, but data transmission delay increases
Solution Approach 1:
The routing function is extracted from the CPU/NC and placed in the dedicated interconnect device. The interconnect device handles all routing decisions based on destination addresses, while CPUs simply send and receive data, eliminating complex jump-point judgment logic from the data path and reducing transmission delay.
Solution Approach 2:
The interconnect device acts as an intermediary between CPUs, handling all data routing operations. This mediator approach allows optimized routing logic to be implemented separately from the CPUs, enabling faster data forwarding without burdening the CPU architecture with complex routing decisions.
3Loss of time
If two dedicated CPU interconnect devices are used for direct CPU-to-CPU connection, then data transmission delay is reduced, but device quantity increases
Solution Approach 1:
The system supports dynamic configuration where interconnect devices can be added or removed based on system requirements. The topology can be adjusted from direct peer-to-peer connections to multi-node configurations, allowing optimization between transmission speed and device quantity depending on specific application needs.
Data Source
AI summary
The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.