CPU Socket Interposer for PCIe Lane Recovery
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Solution Overview
Problem
The increasing complexity of CPU sockets and PCIe lanes in computer systems poses challenges in routing signals and accommodating all necessary connections, particularly in dense server designs, leading to reduced features and performance due to physical constraints.
Innovation Solution
An interposer with a planar substrate and pad array is used to connect CPU sockets, allowing for the reuse of CPU interconnect lanes as serial computer expansion bus connections, such as PCIe, by incorporating retimers to manage signal integrity and a heatsink for thermal management, enabling flexible configuration options.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If x64 lanes are dedicated to the CPU interconnect, then the CPU interconnect is stable and reliable, but only x64 lanes remain available for PCIe connections which limits expansion card connectivity
Solution Approach 1:
The patent implements dynamic lane allocation where the CPU interconnect lanes can be dynamically reassigned to PCIe connections when a CPU is not installed. The system transitions from a static x64 dedicated allocation to a dynamic configuration that adapts based on whether a CPU is present, allowing full x128 lanes to be available for PCIe connections in single-CPU configurations.
Solution Approach 2:
The system changes the operational parameters of the CPU interconnect lanes by detecting CPU presence and reconfiguring the lane assignment. When no CPU is detected in one socket, the lanes that would have been dedicated to CPU interconnect are reparameterized to function as PCIe lanes, effectively changing the system from x64 interconnect + x64 PCIe to x128 PCIe mode.
2Adaptability or versatility
If the number of CPU sockets and PCIe lanes is increased to accommodate greater connectivity, then system features are improved, but physical constraints result in stranding lanes and reduced performance
Solution Approach 1:
The patent introduces an intermediary detection mechanism that monitors CPU presence in each socket and mediates the lane allocation between CPU interconnect and PCIe functions. This intermediary layer abstracts the complexity of lane management, automatically making configuration decisions based on CPU detection without requiring manual intervention or complex routing logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides additional flexibility in computing system configuration, allowing for the recovery of CPU interconnect lanes for use in expansion cards, optimizing performance and reducing costs by enabling single CPU operation with a GPU, beneficial for AI and HPC applications.
Implementation Method 1
a heatsink securable to the first CPU socket, wherein the heatsink includes a bottom surface having a contact area for contacting the interposer, wherein the contact area applies a load to the interposer and conducts heat away from the interposer
Data Source
AI summary
An interposer includes a planar substrate and a pad array formed on a bottom side of the planar substrate to connect with a pin array within a CPU socket. A serial computer expansion bus connector is formed on the top side of the planar substrate and is electronically coupled to a portion of the pad array. The interposer further includes a perimeter structure adapted for securing to a CPU carrier. The interposer may be included in a kit with a heatsink securable to the CPU socket, wherein the heatsink includes a contact area for contacting the interposer and applying a load to the interposer. A printed circuit board assembly may include first and second CPU sockets that are connected by a CPU interconnect, where the interposer may be installed in the first CPU socket and a CPU may be installed in the second CPU socket.