CPU Load Measurement Using Delayed ISR Processing
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Solution Overview
Problem
Existing methods for measuring CPU load are inaccurate and have high overhead, especially when CPU idling and frequency scaling are involved, as they require continuous idle loop spinning or complex instrumentation, leading to increased power consumption and inaccuracy.
Innovation Solution
A low-overhead method that utilizes the built-in capability of some digital signal processors (DSPs) to delay interrupt service routine processing upon CPU wakeup, allowing measurement of idle time by reading the time base before and after the IDLE instruction, and comparing it to total time to calculate CPU load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the idle loop runs continuously to measure CPU load, then load measurement is possible, but power consumption increases and accuracy is lost when CPU is idled
Solution Approach 1:
The patent implements periodic action by using OS-triggered idle loops that execute only when the CPU is actually idle, rather than continuous spinning. The idle loop is activated periodically by the operating system based on workload conditions, allowing accurate measurement of idle time without continuous power consumption. This resolves the contradiction by making the measurement mechanism periodic rather than continuous.
Solution Approach 2:
The patent applies self-service by having the operating system automatically trigger idle loops when appropriate, eliminating the need for continuous active monitoring. The system serves itself by detecting idle conditions and activating measurement only when needed, thereby reducing power consumption while maintaining measurement accuracy during idle periods.
2Use of energy by moving object
If frequency scaling is used to save power, then power consumption decreases, but accurate load measurement becomes difficult
Solution Approach 1:
The patent introduces an intermediary mechanism - the OS-triggered idle loop - that mediates between frequency scaling operations and load measurement requirements. The idle loop serves as an intermediary that can accurately measure idle time even when frequency scaling is active, because it is triggered by the OS which manages the frequency scaling, thereby decoupling the measurement accuracy from the frequency changes.
3Use of energy by moving object
If clock gating is used to halt CPU during idle time, then power consumption decreases, but idle loop calibration becomes unnecessary and measurement approach must change
Solution Approach 1:
The patent applies inversion by changing the measurement approach from active spinning (traditional method) to passive idle loop triggering (new method). Instead of having the CPU actively spin and measure time, the system inverts the approach by allowing the CPU to enter idle state and having the OS trigger measurement loops only when needed. This inversion simplifies the measurement implementation while maintaining accuracy and enabling clock gating.
Data Source
AI summary
An extremely low overhead method calculates CPU load in the presence of both CPU idling and frequency scaling. The method measures time the CPU is idled while waiting for a wakeup. This invention uses a feature in current DSPs with the capability of delaying ISR processing on wake from IDLE. Using this mechanism it is possible to determine the time before IDLE, the time immediately following CPU wakeup, and then run the wakeup ISR. The delta time can be accumulated and compared to total time to determine true CPU load.