CPU Machine Check Bank Error Storm Correlation

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Solution Overview

Problem

Information handling systems face challenges in efficiently correlating and managing machine check error storm events, which can lead to processing slowdowns due to excessive system management interrupts (SMIs) generated from specific machine check banks, causing CPU utilization issues.

Innovation Solution

The system implements a mechanism where the central processing unit (CPU) stores hardware errors in machine check bank registers, generates SMIs, clears older Common Platform Error Record (CPER) entries, and adds new entries to a queue, disabling SMI generation from a bank when the threshold count is exceeded, thereby preventing SMI storms and optimizing CPU usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the system generates SMI for every hardware error in machine check banks, then error detection capability is improved, but CPU utilization deteriorates due to excessive SMI storms

Engineering Contradiction:

Improveerror detection capabilityVSAvoidCPU utilization

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary actions by clearing CPER entries outside a specific timespan before adding new entries, and proactively disables SMI generation when threshold counts are exceeded, preventing SMI storms before they occur

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms by monitoring the number of CPER entries in the queue and dynamically adjusting SMI generation behavior based on the threshold count, creating a closed-loop control system that balances error detection with CPU utilization

Inventive Principle:

Principle #23Feedback

2Loss of information

If the system maintains all CPER entries in the queue, then error record completeness is improved, but memory usage and processing complexity worsen

Engineering Contradiction:

Improveerror record completenessVSAvoidprocessing complexity

Core Design Contradiction:

Loss of informationVSDevice complexity

Solution Approach 1:

The system performs preliminary clearing of CPER entries that fall outside a specific timespan before processing new error records, preventing queue accumulation and reducing processing complexity while maintaining relevant error information

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system dynamically manages the CPER queue by applying time-based filtering and threshold-based SMI disabling, making the error recording system adaptive rather than static, thereby balancing information retention with processing efficiency

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10318455B2System and method to correlate corrected machine check error storm events to specific machine check banks

Publication Date: 2019.06.11 DELL PROD LP

AI summary

An information handling system includes a central processing unit, which in turn includes a system memory and a first processor core. The system memory stores Common Platform Error Record (CPER) entries in a queue. The first processor core stores the hardware error in a bank of a machine check bank register of the first processor core, and generates a system management interrupt (SMI) in response to storing the hardware error in the bank. The central processing unit receives the generated SMI, clears CPER entries within the queue of the system memory that are outside a specific timespan before a corrected machine check error indication associated with the generated SMI is received, adds a CPER entry associated with the corrected machine check error indication to the queue of the system memory, and disables SMI generation from the machine check bank number in response to the number of CPER entries exceeding the threshold count.