CPU Memory Copy Controller for Aligned High-Bandwidth Transfers

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Solution Overview

Problem

Existing memory copy operations in CPUs suffer from low efficiency due to alignment requirements, branch instruction overhead, and limitations in utilizing storage bandwidth, leading to increased power consumption and latency.

Innovation Solution

A CPU design with an instruction decoder, memory copy controller, general-purpose register, bus interface, buffer, adder, and comparator, which allows for efficient memory copy operations by decoding valid instructions, reading and writing data through state machines, and supporting alignment modes, while enabling interruption and multiplexing existing CPU units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software method is used for memory copy, then flexibility and compatibility are improved, but power consumption increases and execution efficiency decreases

Engineering Contradiction:

ImprovecompatibilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The CPU performs memory copy operations autonomously using dedicated hardware circuits (memory copy controller, buffer, adder, comparator) without requiring software intervention or loop execution, thereby reducing power consumption while maintaining flexibility through programmable control

Inventive Principle:

Principle #25Self-service

2Adaptability or versatility

If software method is used for memory copy, then compatibility is improved, but execution efficiency decreases due to instruction bus latency and branch prediction failures

Engineering Contradiction:

ImprovecompatibilityVSAvoidexecution efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent replaces the software-based memory copy mechanism (which relies on instruction fetching, decoding, and execution loops) with a dedicated hardware memory copy controller that operates independently, eliminating instruction bus latency and branch prediction overhead while maintaining compatibility through programmable address and control parameters

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Device complexity

If maximum copy size is limited by CPU register width, then register utilization is optimized, but storage bandwidth utilization decreases

Engineering Contradiction:

Improveregister utilizationVSAvoidstorage bandwidth utilization

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent introduces a buffer as an intermediary component between the CPU registers and external storage, allowing data to be temporarily stored and transferred in large blocks. This enables the system to utilize full storage bandwidth by copying data in chunks larger than register width, while registers continue to hold control parameters (addresses, lengths) without being constrained by width limitations

Inventive Principle:

Principle #24Intermediary (Mediator)

4Productivity

If DMA is used for hardware memory copy, then execution speed is improved, but compatibility and flexibility decrease due to lack of alignment mode support

Engineering Contradiction:

Improveexecution speedVSAvoidalignment mode support

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal memory copy controller that combines the high-speed hardware operation of DMA with the flexibility of software control. The controller can handle various alignment modes by programmatically adjusting address parameters and copy lengths, while maintaining DMA-like performance through dedicated hardware circuits that operate independently of the main instruction stream

Inventive Principle:

Principle #6Universality (Multi-functionality)

5Reliability

If software waits for DMA completion, then data integrity is ensured, but execution efficiency decreases due to inability to suspend or parallelize operations

Engineering Contradiction:

Improvedata integrityVSAvoidexecution efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent enables continuous memory copy operations by allowing the memory copy controller to operate independently and concurrently with other CPU operations. Multiple memory copy instructions can be pipelined or executed in parallel without requiring the CPU to wait for completion, while data integrity is maintained through the buffered transfer mechanism and address validation logic

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20250362917A1CPU capable of quickly processing memory copy instruction and method therefor

Publication Date: 2025.11.27 NANJING QINHENG MICROELECTRONICS CO LTD

AI summary

Disclosed are a CPU capable of quickly processing a memory copy instruction and a method therefor, the CPU comprises: an instruction decoder, a general-purpose register, a memory copy controller, a bus interface, a buffer, an adder and a comparator, the memory copy controller comprises a state machine, the state machine comprises an idle state, a read state and a write state, and in the idle state, the instruction decoder waits for receiving a valid memory copy instruction; in the read state, data of a source address are read through the bus interface and the data are temporarily stored in the buffer; and in the write state, the temporarily stored data from the buffer are written to a target address through the bus interface, the adder is used for updating the address, and the comparator is used for judging whether memory copy is finished.