Master Slave CPU Micro-Program Revision via Auxiliary Interface
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Solution Overview
Problem
Electronic apparatuses with single rewritable memory face limitations in micro-program size constraints and inflexible communication protocols when multiple CPUs are connected through a single interface, requiring a solution to securely revise micro-programs and accommodate varying CPU functions and communication speeds.
Innovation Solution
The apparatus includes a master CPU, a slave CPU, and an analog switch to temporarily connect the CPUs via auxiliary interfaces, allowing the slave CPU to rewrite the micro-program in the master CPU's memory independently, enabling flexible communication protocols and variable speeds while preventing unintended revisions and ensuring error checking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If only one rewritable memory is installed in the apparatus, then the memory size must be greater than twice the size of the new micro-program, but this increases the memory size requirement and cost
Solution Approach 1:
The patent divides the memory system into two separate CPUs: a master CPU that executes the micro-program and a slave CPU that performs the revision operation. This segmentation allows the revision process to occur without requiring the master CPU's memory to be large enough to hold both the old and new micro-programs simultaneously, as the slave CPU handles the temporary storage and transfer operations.
Solution Approach 2:
The slave CPU acts as an intermediary between the host system and the master CPU's memory. It receives the new micro-program from the host, temporarily stores it in its own memory, and then transfers it to the master CPU's memory. This intermediary role eliminates the need for the master CPU's memory to accommodate the entire revision process internally.
2Adaptability or versatility
If multiple CPUs are connected through a single interface or bus, then all CPUs must use a common protocol and fixed communication speed, but this reduces flexibility for different CPU functions and speeds
Solution Approach 1:
The patent assigns different interface types to different CPUs: the slave CPU is equipped with both an outer interface for host communication and an inner interface for CPU-to-CPU communication, while the master CPU has only the inner interface. This local differentiation allows each CPU to have interfaces optimized for its specific function without requiring all CPUs to support all interface types.
Solution Approach 2:
The system dynamically assigns the bus master position between the master CPU and slave CPU depending on the operational phase. During normal operation, the master CPU holds the bus master position. During revision operations, the slave CPU temporarily takes the bus master position to transfer data. This dynamic role assignment allows flexible communication protocols and speeds tailored to different operational requirements.
Data Source
AI summary
An electronic apparatus is disclosed, where the apparatus revises the micro-program thereof reliably. The apparatus provides a master and slave CPUs each having a memory. The micro-program to be revised is temporarily set in the memory of the slave CPU. Interrupting the master CPU, and connecting the slave CPU with the master CPU via an auxiliary interface independent of the inner interface (bus), the micro-program to be revised and stored in the memory of the slave CPU is transferred to the memory of the master CPU through the auxiliary interface. Auxiliary interface is cut during the normal operation of the master CPU.