CPU Module Reset Signal Blocking for Seamless Storage Upgrades
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Solution Overview
Problem
During a software upgrade of a data storage system, the existing technologies cause interruptions in data transfer between a host computer/server and storage media, as the processor complex resets, leading to downtime and potential data loss, as all attached PCI-Express devices reset, disrupting ongoing operations.
Innovation Solution
A data storage system with a pair of CPU modules that produce different types of reset signals, where a software reset signal during an upgrade inhibits port disabling, allowing the second module to take over the IO transfer, ensuring uninterrupted data processing by blocking resets to PCI-Express devices and rerouting data through an I2C interface, enabling seamless transitions during upgrades.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a processor complex resets during a software upgrade, then the software can be updated, but all attached PCI-Express devices reset, causing interruptions in data transfer
Solution Approach 1:
The system separates the processor complex reset function from the PCI-Express device reset function by introducing a reset signal blocking mechanism. The processor complex can reset independently without forcing PCI-Express devices to reset, achieved by blocking reset signals to these devices during processor resets. This segmentation allows software upgrades while maintaining data transfer continuity.
Solution Approach 2:
A reset signal blocking mechanism acts as an intermediary between the processor complex and PCI-Express devices. When the processor complex needs to reset for software upgrades, this intermediary blocks the reset signal from propagating to PCI-Express devices, preventing their reset and maintaining ongoing data transfers. The intermediary enables controlled signal propagation based on system state.
2Adaptability or versatility
If the processor complex resets during an IO transfer, then software upgrades can occur, but the IO transfer is interrupted and host computer/server operations are disrupted
Solution Approach 1:
The system performs preliminary actions by detecting when an IO transfer is in progress before the processor complex resets. When such a condition is detected, the system proactively blocks reset signals to PCI-Express devices and reroutes IO transfers through alternative paths. This preliminary protection ensures that ongoing data processing operations continue uninterrupted during software upgrades.
Solution Approach 2:
The system dynamically changes the state of reset signal blocking based on system conditions. When software upgrades are needed, the reset blocking parameter is activated to prevent PCI-Express device resets. When normal operation is detected, the blocking is deactivated. This parameter change allows the system to adapt between software maintenance mode and normal productivity mode.
3Adaptability or versatility
If a system reset signal is produced during a software upgrade, then the processor complex can be reset, but the port is disabled and failover to another CPU module is required
Solution Approach 1:
The system applies preliminary anti-action by blocking reset signals to ports and PCI-Express devices before the processor complex reset is executed during software upgrades. This preemptive blocking prevents the automatic port disabling and failover behavior that would otherwise occur. By counteracting the reset signal propagation in advance, the system maintains operational transparency and prevents unnecessary failover events.
Data Source
AI summary
A data storage system having a pair of CPU modules each one of having a port coupled to a host computer/server and a storage medium for transferring data during an IO transfer. Each one of the modules produces different types of reset signals, one of such types being a software reset signal produced during a software upgrade of the module and other types being produced for events other than during a software upgrade, The other types produced by a first one of the modules disables the port of the first one of the modules; whereas, in response the software reset signal produced by the first one of the modules during an IO transfer, a second one of the modules couples the port of the first one of the modules to the second one of the modules to enable the IO transfer to be processed by the second one of the modules.