CPU-MRAM and DRAM Storage Segmentation for Fast Boot
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Solution Overview
Problem
Current information processing systems for multi-function image forming devices lack efficient power management and data retention capabilities, leading to slow boot times and unreliable operations during power resets.
Innovation Solution
The system incorporates a CPU-MRAM module for non-volatile data retention and a CPU-DRAM module for volatile data, along with a CPU-ROM module for program storage, enabling selective IPL execution and optimized communication conditions through a PCIe bus and I2C buses, allowing for faster boot processes and improved power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional ROM boot methods are used, then system simplicity is maintained, but boot time is excessive (approximately 3.4 seconds slower)
Solution Approach 1:
The patent segments the storage system into multiple distinct components: a first non-volatile memory (ROM) for storing boot programs, a second non-volatile memory (MRAM) for storing communication conditions and data, and a volatile memory (DRAM) for temporary data storage. This segmentation allows each memory type to be optimized for its specific function, enabling faster boot times through selective IPL execution while maintaining system organization and manageability.
Solution Approach 2:
The patent implements preliminary action by pre-storing communication conditions and operational data in the MRAM before power cycles. This allows the system to rapidly restore operational state after power reset without requiring full re-initialization, significantly reducing boot time while keeping the overall system architecture relatively simple.
2Speed
If volatile memory (DRAM) is used for data storage, then write speed is improved, but data loss occurs during power resets
Solution Approach 1:
The patent applies local quality by assigning different memory types to different functional requirements: DRAM is used specifically for areas requiring high write speed (temporary data and working memory), while MRAM is used for areas requiring data retention (communication conditions and critical operational data). This localized assignment of memory characteristics allows the system to optimize for both speed and reliability in appropriate locations without compromising overall system performance.
3Reliability
If non-volatile memory (MRAM) is used for data retention, then data retention during power reset is improved, but write speed is reduced compared to volatile memory
Solution Approach 1:
The patent segments the storage hierarchy into multiple levels with different performance characteristics. The MRAM serves as a non-volatile cache layer that retains data without power, while the DRAM provides high-speed volatile storage. This segmentation allows the system to leverage the strengths of each memory type: MRAM for reliability and DRAM for speed, eliminating the need to choose one compromise solution.
Solution Approach 2:
The patent merges multiple memory technologies (ROM, MRAM, and DRAM) into a unified storage hierarchy that functions as an integrated system. This combination allows the system to simultaneously achieve data retention capabilities of non-volatile memory and high write speeds of volatile memory by appropriately distributing data across the different memory types based on their characteristics.
4Use of energy by moving object
If multiple memory types are integrated, then power management efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic power management by enabling selective activation of different memory components based on operational requirements. The system can enter low-power states by deactivating portions of the memory system when full capacity is not needed, while maintaining the ability to rapidly activate required components. This dynamic approach improves power efficiency without requiring permanent complex control circuitry for all possible states.
Data Source
AI summary
An information processing apparatus includes an execution unit that executes a program, a main storage unit that includes a first non-volatile memory which is readable and writable and is capable of retaining stored information even when no power is supplied and is provided with a first storage area which stores the program executed by the execution unit and a second storage area which stores data generated by the execution of the program by the execution unit, a connection unit that connects the execution unit and the main storage unit, and a condition storage unit that includes a second non-volatile memory which is readable and writable and is capable of retaining stored information even when no power is supplied and stores conditions which are set by the connection unit to transmit and receive the program and the data between the execution unit and the main storage unit.