Offloading CPU Tasks to Universal Digital Blocks
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Solution Overview
Problem
Central processing units (CPUs) in System on Chip (SoC) devices face increased burden and power consumption due to performing complex calculations, leading to delays and resource inefficiencies.
Innovation Solution
Distributing processing tasks to a network of universal digital blocks (UDBs) connected via DMA and programmable logic, allowing the CPU to offload tasks and reduce processing resource usage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the CPU performs complex calculations, then calculation accuracy is maintained, but processing speed decreases and power consumption increases
Solution Approach 1:
The patent divides the SoC processing system into multiple independent processing units including the CPU and specialized peripheral function engines (PFEs). Each PFE is dedicated to specific complex calculation tasks such as square root, automatic gain control, and root mean square calculations. This segmentation allows the CPU to offload these computationally intensive tasks to specialized units, maintaining calculation accuracy while significantly improving processing speed and reducing power consumption.
2Adaptability or versatility
If the CPU performs multiple operations, then system functionality is maintained, but task completion time increases
Solution Approach 1:
The system is segmented into multiple parallel processing paths with dedicated PFEs for different function types. This allows simultaneous execution of multiple operations without sequential bottlenecks, reducing overall task completion time while maintaining full system functionality.
Solution Approach 2:
Complex calculation functions are pre-configured and hardcoded into the peripheral function engines during chip fabrication. This preliminary action enables these functions to execute immediately without requiring CPU interpretation or setup, significantly reducing task completion time for routine operations.
3Power
If the CPU performs complex calculations, then processing capability is maintained, but power consumption increases
Solution Approach 1:
The processing system is segmented into the CPU for general-purpose operations and specialized PFEs for specific complex calculations. Each PFE is optimized for its designated function with dedicated hardware circuits, requiring significantly less power than CPU-based execution. This segmentation maintains overall processing capability while reducing total power consumption through specialized optimization.
Solution Approach 2:
The patent implements hardware copies of complex calculation algorithms directly in the PFEs as dedicated logic circuits. Instead of the CPU repeatedly executing software instructions for the same calculations, pre-configured hardware copies perform these operations instantly with minimal power consumption, especially for repetitive tasks like square root or RMS calculations.
Data Source
AI summary
An apparatus includes an array of universal digital blocks (UDBs) and a central processing unit (CPU) coupled to the array of UDBs via a bus. The UDBs may be coupled together to perform tasks, operations or functions that may be offloaded from the CPU to the array of UDBs.