Stepwise CPU Overclocking via BIOS Interrupts

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Solution Overview

Problem

Existing methods for overclocking CPUs do not load the operating system at the steadiest CPU frequency and do not perform an overclocking procedure to change the Front Side Bus (FSB) frequency of the CPU after the operating system is loaded, requiring recalculations when system parameters change.

Innovation Solution

A method that sets a second FSB frequency through the BIOS, determines intermediate frequencies in an arithmetic progression, loads the operating system at the default FSB frequency, and uses interruption signals to incrementally change the FSB frequency to the second frequency, allowing the operating system to resume control after each step.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the CPU is overclocked by changing FSB frequency after the operating system is loaded, then the CPU can operate at optimized frequencies, but the system stability may be compromised due to frequent parameter changes

Engineering Contradiction:
Improveoverclocking efficiencyVSAvoidsystem stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The overclocking process is divided into discrete stages with intermediate frequency levels. The FSB frequency is changed stepwise through multiple interruption cycles rather than in a single large jump, allowing the system to stabilize at each intermediate level before proceeding to the next frequency level.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses periodic interruption signals to control the frequency changing process. The chipset generates interruption signals at predetermined intervals, allowing the BIOS to execute frequency changes in a controlled periodic manner rather than continuously, thereby maintaining system stability during the overclocking process.

Inventive Principle:
Principle #19Periodic action

2Productivity

If the FSB frequency is changed frequently during overclocking, then the CPU can reach higher frequencies, but the need for recalculations increases when system parameters change

Engineering Contradiction:
Improveoverclocking speedVSAvoidrecalculation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by establishing a stable operating system load at the default FSB frequency before initiating the overclocking process. This preliminary stable state allows subsequent frequency changes to be made more efficiently without requiring frequent recalculations, as the system parameters are already optimized for the initial frequency level.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the operating system is loaded at the default FSB frequency, then the system boots stably, but the overclocking process cannot begin until after loading

Engineering Contradiction:
Improveboot stabilityVSAvoidtime to reach target frequency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent introduces dynamic control during the boot process by using interruption signals that can trigger frequency changes at specific moments. The system transitions from a static default frequency during boot to a dynamic multi-stage frequency adjustment process after loading, allowing the overclocking to begin immediately without requiring separate manual intervention.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8245075B2Overclocking CPU with stepwise increase in frequency by BIOS gaining control upon interrupt generated at predetermined intervals
Publication Date: 2012.08.14 MSI COMPUTER (SHENZHEN) CO LTD
  • US8245075B2 patent drawing
  • US8245075B2 patent drawing
  • US8245075B2 patent drawing

AI summary

A method for overclocking a central processing unit (CPU) of a computer motherboard is disclosed. Step A is to set a second frequency of front side bus (FSB) by an operating interface of BIOS. Step B is to determine FSB frequency Fn at each of N stages according to a difference between a first frequency and the second frequency. Step C is to load the CPU with an operating system by booting the CPU at the first frequency of FSB, and send an interruption signal to the CPU from a chipset at predetermined intervals upon completion of the loading of the operating system so as to allow the BIOS to gain control over the CPU, and execute step D by the CPU on each of N occasions of interruption until the FSB frequency of the CPU is changed to the second frequency. Step D is to execute the BIOS by the CPU on the nth occasion of interruption such that the CPU operates at the FSB frequency Fn, and allow the operating system to resume control over the CPU.