CPU Overcommit for SMP Virtual Machines with Counter-Based Preemption

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Solution Overview

Problem

In virtualization environments with Symmetric Multi-Processing (SMP) and overcommit, SMP VMs can unfairly monopolize CPU resources, leading to inefficiencies and reliability issues due to frequent or lengthy latency caused by preempting tasks from other VMs, which disrupt critical-section operations.

Innovation Solution

Implementing a counter mechanism on physical CPUs to temporarily disable hypervisor preemption during critical-section operations, allowing SMP VMs to selectively prevent interruptions until the counter expires, ensuring timely re-enablement of preemption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If SMP VMs are allowed to use multiple PCPUs simultaneously with overcommit, then computing efficiency and resource utilization are improved, but critical-section operations may be disrupted by preempting tasks from other VMs causing latency and reliability issues

Engineering Contradiction:
Improvecomputing efficiencyVSAvoidcritical-section operation reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by setting a counter to a non-zero value before executing critical-section operations. This pre-established counter serves as a protective mechanism that proactively prevents preemption interruptions during time-sensitive operations, ensuring that critical sections complete without disruption while maintaining overall system productivity through controlled preemption elsewhere.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If preemption is allowed to occur freely on PCPUs, then system flexibility and resource sharing among VMs are improved, but latency is increased due to frequent interruptions of critical operations

Engineering Contradiction:
Improvesystem flexibilityVSAvoidlatency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The counter is established in advance before critical operations begin, creating a pre-arranged protection window. This preliminary setup allows the system to maintain flexibility for non-critical operations while proactively preventing preemption during time-sensitive critical sections, thereby reducing latency without sacrificing overall system adaptability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The counter operates as a periodic control mechanism that temporarily disables preemption during critical sections and allows it during non-critical periods. This periodic switching between protected and flexible states enables the system to balance latency reduction with maintained adaptability across different operational phases.

Inventive Principle:
Principle #19Periodic action

3Reliability

If SMP VMs monopolize CPU resources during critical operations, then operational reliability is improved, but resource sharing efficiency and productivity of other VMs deteriorate

Engineering Contradiction:
Improveoperational reliabilityVSAvoidresource sharing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By setting the counter to a non-zero value before entering critical sections, the system proactively reserves CPU resources only when necessary for reliability. This preliminary reservation ensures critical operations complete without interruption while minimizing the duration and scope of resource monopolization, allowing other VMs to efficiently utilize resources during non-critical periods.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12411704B2Efficient central processing unit overcommit for virtual machines with symmetric multi-processing
Publication Date: 2025.09.09 RED HAT LLC
  • US12411704B2 patent drawing
  • US12411704B2 patent drawing
  • US12411704B2 patent drawing

AI summary

Efficient central processing unit overcommit for virtual machines with symmetric multi-processing may be provided by, in response to receiving a preemption-disable request on behalf of a virtual machine (VM) running on a physical central processing unit (PCPU), initiating a counter on the PCPU; in response to receiving a preempting task from a hypervisor to perform on the PCPU, checking a counter status for the counter; in response to the counter status being active: performing an ongoing task from the VM on the PCPU; and delaying performance of the preempting task until the counter status is inactive.