CPU Parser Instructions for Parallel TLV Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing network protocol parsing technologies face challenges in achieving high performance and flexibility to handle variable-length headers, sub-structures like Type Length Value (TLVs), and multiple layers of encapsulation while supporting a wide variety of protocols.
Innovation Solution
The PANDA Parser employs a system and method for parallelizing serial processing pipelines using a parser engine that processes multiple stages concurrently, leveraging hardware accelerations and alternative memory access methods, with a parser engine that utilizes parse nodes, protocol tables, and metadata extraction to handle protocol headers and sub-headers efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial processing pipeline is used for protocol parsing, then processing stages can be completed sequentially with simple dependency management, but parsing performance and throughput are limited due to sequential execution
Solution Approach 1:
The protocol parsing pipeline is divided into multiple independent stages (e.g., Ethernet parsing, IP parsing, TCP parsing) that can be executed in parallel. Each stage processes specific protocol layers and produces metadata that can be consumed by subsequent stages, enabling concurrent processing while maintaining manageable complexity through clear stage boundaries.
Solution Approach 2:
The patent transitions from sequential (1D) processing to parallel (multi-dimensional) processing by introducing multiple threads that can execute simultaneously. This dimensional change allows different protocol layers to be parsed concurrently, significantly improving throughput while the threading model provides a structured approach to managing the increased complexity.
2Adaptability or versatility
If fixed-length protocol headers are parsed, then parsing is simple and fast, but flexibility to handle variable-length headers and sub-structures like TLVs is lost
Solution Approach 1:
The parsing system dynamically adapts to variable-length protocol headers by using length fields and pointers to determine the actual size of each header. The parser can adjust its behavior based on the parsed data, allowing it to handle both fixed-length and variable-length headers efficiently. This dynamic approach maintains high parsing speed while achieving the needed flexibility.
Solution Approach 2:
The patent introduces an intermediary metadata structure that stores parsed information from protocol layers. This metadata acts as a mediator between the parsing stages and the rest of the processing pipeline, enabling flexible handling of variable-length headers and sub-structures like TLVs without compromising parsing performance. The metadata layer abstracts the complexity of variable-length parsing from the overall system.
3Loss of time
If multiple protocol layers are processed sequentially, then dependency management is straightforward, but latency increases due to sequential execution
Solution Approach 1:
The parser performs preliminary parsing of protocol layers as soon as data becomes available, without waiting for the entire packet to be received or for subsequent layers to be fully processed. This preliminary action enables overlapping of parsing operations across different layers, reducing latency. The threading model allows earlier stages to proceed independently while later stages are prepared in advance.
Solution Approach 2:
The patent ensures continuous useful action by maintaining multiple parsing threads that can execute simultaneously. Instead of waiting for one layer to complete before starting the next, the system continuously processes available data across all layers. This continuity is achieved through proper synchronization mechanisms that coordinate thread execution while maximizing parallel processing efficiency.
4Productivity
If conventional packet processing is used, then existing codebases can be leveraged, but performance is limited by standard CPU processing speeds and memory access methods
Solution Approach 1:
The patent replaces conventional CPU-based mechanical processing with hardware-accelerated parsing. By implementing dedicated parsing hardware or using CPU instructions optimized for packet processing, the system achieves significantly higher processing speeds. This substitution of the processing mechanism maintains compatibility with existing protocols while dramatically improving performance.
Solution Approach 2:
The parsing system is designed with universal components that can handle multiple protocol types and processing scenarios. The hardware acceleration framework is built to support various packet processing tasks, making it adaptable to different network protocols and processing requirements. This universality allows the system to leverage hardware acceleration for multiple functions without requiring separate specialized hardware for each protocol.
Data Source
AI summary
A system and method for a protocol parser that has native support for parsing TLVs and flag-fields and allow users to code in a language convenient to them and leverage standard tool chains and tools. The same parser source can be compiled to arbitrary software and hardware targets without code change and provide the highest performance possible given its capabilities.