CPU PLL Phase Selection for 1 MHz-Step Overclocking
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Solution Overview
Problem
Current overclocking methods for CPUs lack simplicity, particularly in achieving a 1 MHz-step resolution across all frequencies, requiring complex calculations and limiting users' ability to precisely overclock CPUs to match modern component requirements.
Innovation Solution
A timing circuit system with a CPU PLL and phase selection circuit that adjusts a fractional N-divider feedback circuit, allowing users to programmatically adjust CPU clock signals in 1 MHz increments independently of the CPU output frequency, enabling precise overclocking without complex calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional overclocking methods are used, then users can increase CPU frequency, but the overclocking resolution varies with output frequencies and requires complex calculations to achieve precise 1 MHz-step resolution
Solution Approach 1:
The patent implements dynamic phase selection in the PLL feedback circuit that automatically adjusts based on the current CPU output frequency. The system dynamically switches between different phase configurations (0°, 120°, 240°) to maintain consistent 1 MHz-step resolution across all frequency ranges, eliminating the need for manual complex calculations by users.
Solution Approach 2:
The patent changes the operational parameters of the PLL feedback circuit by introducing phase selection capability. By varying the phase parameter dynamically according to the output frequency, the system maintains constant overclocking resolution. The phase selection circuit modifies the feedback signal phase to compensate for frequency-dependent resolution variations inherent in traditional designs.
2Adaptability or versatility
If traditional PLL feedback circuits are used, then the system operates at various CPU frequencies, but the overclocking resolution is not consistent and cannot achieve 1 MHz-step resolution at all frequencies
Solution Approach 1:
The phase selection circuit dynamically adapts its configuration based on the current operating frequency. The system monitors the CPU output frequency and automatically selects the appropriate phase shift (0°, 120°, or 240°) to maintain consistent 1 MHz-step resolution across the entire frequency spectrum, from base frequencies to overclocked frequencies.
Solution Approach 2:
The patent creates a universal overclocking solution that works across all CPU frequencies through the phase selection mechanism. The feedback circuit is designed to handle multiple frequency ranges uniformly by selecting appropriate phase configurations, making the 1 MHz-step resolution achievable regardless of the base frequency or target overclock frequency.
Data Source
AI summary
A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency.