CPU Power Level Transition from C3 to C2 for Bus Master Requests
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Solution Overview
Problem
The existing power management systems, such as ACPI, inefficiently recover CPUs from the C3 power level to C0 for processing bus master requests, leading to unnecessary power consumption as they stay at the C0 level until the next power-saving condition is applied, even though the C2 level would suffice for snooping functions.
Innovation Solution
A power saving method and system that switches the CPU from the C3 power level to a transitional C0 level, then to C2 level for processing bus master requests, with the arbitrator disabled during the transition, and enables it only when necessary to reduce power consumption by avoiding redundant operations at the C0 level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU recovers to C0 power level from C3 to process bus master requests, then the CPU can execute snooping functions, but the CPU consumes more power unnecessarily by staying at C0 level
Solution Approach 1:
The patent changes the CPU power level parameter from the conventional C0 level to C2 level when processing bus master requests. This parameter change allows the CPU to maintain the necessary snooping functionality while consuming less power, as C2 level provides sufficient performance for bus master request processing without the excessive power consumption of C0 level.
Solution Approach 2:
The patent introduces dynamic power level adjustment based on the specific task requirements. Instead of always recovering to the fixed C0 level, the CPU dynamically selects the appropriate power level (C2 for bus master requests, C0 for general operations), optimizing the balance between performance and power consumption in real-time.
2Productivity
If the CPU stays at C0 power level after processing requests, then the CPU is ready for next operations, but power consumption increases due to unnecessary time at higher power level
Solution Approach 1:
The patent implements periodic power level adjustment where the CPU transitions to C0 level only when actually needed for general operations, rather than remaining at C0 continuously. This periodic activation reduces energy loss by minimizing the time spent at higher power consumption levels while maintaining productivity through timely transitions to C0 when required.
Data Source
AI summary
For saving power of a central processing unit at a C3 power level upon processing a bus master request from a peripheral device, an arbitrator is disabled from transmitting any request to the central processing unit at the C3 power level. Afterwards, in response to a bus master request, the central processing unit is switched from the C3power level to a transitional C0 power level while keeping the arbitrator disabled, and then switched from the transitional C0 power level to a C2 power level while enabling the arbitrator to process the bus master request.