CPU Power Control via Transient Budget and DCVS

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Solution Overview

Problem

Current methods for controlling power in multicore CPUs in portable computing devices are inefficient in managing transient workloads, leading to potential task failures due to lag in tracking workload changes and Quality of Service (QoS) requirements.

Innovation Solution

The implementation of a dynamic clock and voltage scaling (DCVS) algorithm that monitors CPU performance and adjusts clock frequency to meet transient performance deadlines, ensuring timely responses by calculating an effective transient budget and scheduling jumps to higher performance levels to maintain QoS guarantees.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If dynamic clock and voltage scaling (DCVS) is used to reduce power consumption, then energy efficiency improves, but the system cannot meet transient performance deadlines due to lag in tracking workload changes

Engineering Contradiction:
Improvepower consumptionVSAvoidtransient performance deadline
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The system performs preliminary actions by calculating an effective transient budget that predicts the time needed to reach higher performance levels. This allows the DCVS algorithm to proactively schedule frequency jumps before transient workloads occur, ensuring that performance deadlines are met while still maintaining low power consumption during idle periods. The transient budget computation anticipates future performance needs rather than reacting to them.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts CPU clock frequency based on real-time workload conditions by implementing a deadline-monotonic DCVS algorithm. The frequency scaling is dynamically controlled to meet transient performance deadlines while minimizing power consumption. The system transitions between different frequency levels adaptively, making the power consumption dynamic rather than static, thus resolving the contradiction between low power and high performance.

Inventive Principle:
Principle #15Dynamics

2Speed

If CPU frequency is increased to meet transient workloads, then response time improves, but power consumption increases

Engineering Contradiction:
Improveresponse timeVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The system uses periodic action by implementing deadline-monotonic frequency scaling that activates only when transient performance deadlines require it. Instead of maintaining high frequency continuously, the CPU operates at low frequency during idle periods and periodically jumps to higher frequencies only when needed to meet deadlines. This periodic activation of high-performance mode minimizes overall power consumption while ensuring timely response to transient workloads.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system changes the CPU frequency parameter dynamically based on workload conditions and transient deadline requirements. The DCVS algorithm computes the effective transient budget and adjusts the clock frequency parameter accordingly - maintaining low frequency for power efficiency during idle periods, and increasing frequency only when transient workloads require improved response time. This parameter change strategy optimizes the trade-off between speed and power consumption.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If traditional power management is used, then implementation simplicity is maintained, but task failures occur due to inability to track workload changes timely

Engineering Contradiction:
Improveimplementation simplicityVSAvoidtask completion
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system implements feedback mechanisms by continuously monitoring workload conditions and using this information to adjust CPU frequency in real-time. The deadline-monotonic DCVS algorithm incorporates feedback from performance deadline requirements and workload characteristics to make informed frequency scaling decisions. This feedback loop ensures that the system can track workload changes timely and adjust performance levels accordingly, preventing task failures while maintaining reasonable implementation complexity through structured control logic.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8909962B2System and method for controlling central processing unit power with guaranteed transient deadlines
Publication Date: 2014.12.09 QUALCOMM INC
  • US8909962B2 patent drawing
  • US8909962B2 patent drawing
  • US8909962B2 patent drawing

AI summary

A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget.