CPU Power Management via Hardware Arbiter and SMI Wake
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Solution Overview
Problem
Conventional power management systems for CPUs, especially in portable computers, result in excessive power consumption and reduced operational time due to inefficiencies in transitioning between low power sleep states, as the CPU must wake and return to a higher power state to process interrupts and bus master requests, leading to prolonged time in less efficient states.
Innovation Solution
A method and system that utilize a chip to send control signals and system management interrupts to drive the CPU from a non-snooping sleep state to a normal executing state, enabling an arbiter to process bus master requests outside operating system control, and then return to the sleep state using a system management interrupt routine, avoiding immediate operating system control and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the CPU enters C3 state to save power, then power consumption is reduced, but the CPU cannot process bus master requests efficiently
Solution Approach 1:
The patent segments the power management states into C3 state for power saving and introduces a specialized wake-up mechanism for bus master requests. The arbiter is divided into two parts: a first part that operates in C3 state to manage bus master requests, and a second part that activates only when needed. This segmentation allows the system to maintain power saving capabilities while adding specialized processing functionality.
Solution Approach 2:
The patent introduces an intermediary mechanism (the first part of the arbiter and the wake-up signal generation circuit) that mediates between the C3 power-saving state and the need to process bus master requests. This intermediary allows the CPU to remain in C3 state while still enabling request processing through a controlled wake-up mechanism, resolving the contradiction between power saving and processing capability.
2Productivity
If the CPU wakes from C3 state to process bus master requests, then requests can be handled, but additional power is consumed and time is lost
Solution Approach 1:
The patent applies preliminary action by having the first part of the arbiter continuously monitor and prepare bus master requests in the C3 state, rather than waiting for the CPU to wake. The wake-up signal generation circuit is pre-configured to immediately generate wake-up signals when bus master requests are detected, eliminating the need for the CPU to fully wake, process, and then return to C3 state for each request.
Solution Approach 2:
The patent enables continuity of useful action by allowing the arbiter's first part to continuously manage bus master requests while the CPU remains in C3 state. The second part of the arbiter can continuously prepare wake-up signals without interrupting the C3 state, creating a continuous useful action that eliminates the stop-start cycle of waking and sleeping for each request.
3Reliability
If the operating system controls CPU wake-up, then standard power management is maintained, but the CPU cannot return to C3 state quickly enough
Solution Approach 1:
The patent extracts the wake-up control function from the operating system and places it in dedicated hardware circuits (the wake-up signal generation circuit and the second part of the arbiter). This extraction allows the CPU to wake and return to C3 state quickly through direct hardware control, bypassing the slower operating system-based power management procedures while maintaining reliability through dedicated hardware implementation.
Data Source
AI summary
A method for power management of a CPU and a system thereof, which drive the CPU to enter a more efficient power saving state are disclosed. A chip of the present invention sends a first control signal to drive the CPU to wake from a non-snooping sleep state and enter a normally executing instruction state as well as a system management mode to execute a system management interrupt routine. Then the chip enables an arbiter to transmit a bus master request to the CPU for processing. After completing the processing of the bus master request, the chip disables the arbiter and the CPU drives the chip to send a second control signal to drive the CPU to return to the non-snooping sleep state according the system management interrupt routine.