CPU Power State Control for Deadline-Aware Energy Reduction
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Solution Overview
Problem
Existing methods fail to sufficiently reduce the power consumption of Central Processing Units (CPUs) during transitions between active and power saving states, leading to increased energy usage due to high current flow upon returning to an active state, and struggle to balance power saving with meeting processing deadlines.
Innovation Solution
A method that determines an optimal power saving state and operational frequency for the CPU based on the time period and data processing requirements, using a combination of power saving states and frequencies to minimize total power consumption while ensuring timely completion of processing tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the CPU transitions to a power saving state, then power consumption is reduced, but the CPU cannot meet processing deadlines due to slow wake-up and execution
Solution Approach 1:
The patent applies dynamics by making the CPU's operational state flexible and adjustable. Instead of fixed power saving or active states, the system dynamically transitions between multiple intermediate operational states (S0-S3) based on real-time workload characteristics, allowing the CPU to adapt its power consumption and performance levels to match actual processing requirements while meeting deadlines
Solution Approach 2:
The patent changes the parameter of CPU operational frequency and power state continuously. By introducing multiple intermediate operational states with varying frequency levels between full active and deep sleep states, the system can fine-tune power consumption and performance parameters to optimize the trade-off between energy saving and deadline adherence
2Productivity
If the CPU operates at high frequency to meet deadlines, then processing speed is improved, but power consumption increases significantly
Solution Approach 1:
The system dynamically adjusts CPU frequency and operational state based on real-time workload analysis. By continuously monitoring task characteristics and transitioning between multiple operational states (S0-S3), the CPU operates at high frequency only when necessary to meet deadlines, otherwise maintaining lower frequency to reduce power consumption
Solution Approach 2:
The patent applies partial action by using intermediate operational states that provide partial processing capability rather than always operating at full capacity. The CPU can handle less critical tasks at reduced frequency (partial action) while reserving full capacity for time-critical operations, optimizing the balance between productivity and energy consumption
3Loss of energy
If the CPU frequently transitions between active and power saving states, then energy efficiency is improved, but system complexity increases due to state management overhead
Solution Approach 1:
The patent segments the CPU's operational spectrum into multiple discrete states (S0-S3) rather than using a single binary active/sleep transition. This segmentation allows granular control over power consumption levels and simplifies transition management by providing intermediate states that reduce the frequency and complexity of state changes while maintaining energy efficiency
Data Source
AI summary
A method of controlling a processor includes determining an operational mode of the processor in a time period and an operational frequency of the processor in second data processing based on a completion deadline of the second data processing and an amount of data processing in the second data processing which is performed by the processor after first data processing is completed by the processor, the time period being from completion of the first data processing to start of the second data processing, controlling the processor in the determined operational mode after the first data processing is completed by the processor, and performing the second data processing using the processor that operates with the determined operational frequency after the controlling of the processor in the operational mode.