CPU Power Supply Switching via Clock Gating for Low Latency Retention
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Solution Overview
Problem
Conventional low power modes in computing systems sacrifice latency for power saving, and existing hardware-based solutions for reducing leakage power consumption in CPUs are inefficient due to increased latency and reliance on software control.
Innovation Solution
A system and method that automatically switches a CPU to a low power retention mode using architectural clock gating, where a detection module monitors the clock enable signal to switch the CPU from a higher to a lower power supply output, reducing leakage power consumption with minimal latency through hardware implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the CPU is placed in conventional low power mode with clock gating, then dynamic power consumption is reduced, but leakage power consumption remains significant and latency increases
Solution Approach 1:
The patent changes the power supply voltage parameter from full voltage to a lower retention voltage when the CPU enters idle state. This allows the CPU to maintain minimal functionality (retaining register contents) while significantly reducing leakage power consumption compared to conventional clock-gated modes that operate at full voltage.
Solution Approach 2:
The patent implements dynamic power supply switching that automatically adjusts the power voltage based on CPU operational state. The system transitions between full power and retention power modes dynamically, optimizing the balance between performance and power consumption without fixed latency penalties.
2Loss of energy
If software-based power saving measures are implemented, then leakage power consumption is reduced, but latency at mode entry and exit increases
Solution Approach 1:
The patent replaces software-based power control mechanisms with hardware-level automatic switching circuitry. The detection module and power switching circuitry operate autonomously at the hardware level, eliminating the need for software intervention and thereby reducing latency while achieving power savings.
Solution Approach 2:
The system performs self-service power management by automatically detecting CPU idle states through the detection module and autonomously switching power supplies without external software control. This self-managed approach eliminates software overhead and reduces mode transition latency.
3Reliability
If the CPU remains powered at full voltage during idle state, then performance is maintained, but power consumption increases
Solution Approach 1:
The patent changes the power supply voltage parameter from full operating voltage to a lower retention voltage during idle states. This parameter change allows the CPU to maintain essential functionality (register retention) while significantly reducing power consumption, thus optimizing the balance between performance consistency and energy efficiency.
Data Source
AI summary
Method and Apparatus for automatically switching to a low power retention mode based on architectural clock gating is disclosed. In some implementations, a system includes a central processing unit (CPU), comprising a clock gating cell configured to receive a clock enable signal. The system further includes a switching module configured to monitor the clock enable signal and to cause a power manager to switch the CPU from a first power supply output to a second power supply output in response to the clock enable signal changing from a first state to a second state.