CPU Scheduler for C6-State Power Management
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Solution Overview
Problem
Current CPU power management techniques, such as ACPI C-states, are inefficient in eliminating static power consumption, especially with advanced CPU manufacturing processes, and transitioning in and out of low-power states like C6 (zero-power state) is not effectively managed to maximize power savings.
Innovation Solution
A method and system for scheduling tasks to execute on processing units, involving a scheduler that tracks idle-state residency and power-states of processing units, allowing for efficient transition to and from the C6-state by determining available units, waking up necessary units with inter-processor interrupts, and managing power-states to optimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If CPU transitions to low-power states (C1-C5) to reduce dynamic power consumption, then power savings are achieved, but static power consumption is not completely eliminated
Solution Approach 1:
The patent introduces a new power state (C6/0V-state) that represents a fundamental phase transition from partial power reduction to complete power elimination. By transitioning the processor core to a zero-power state where voltage is reduced to 0V and clock is uncoupled, the system achieves complete elimination of both dynamic and static power components, rather than merely reducing them as in traditional C-states.
2Loss of energy
If CPU enters C6-state to eliminate all power consumption, then maximum power savings are achieved, but transition time and system complexity increase
Solution Approach 1:
The patent segments the power management control into two independent parts: voltage control and clock control. By separately managing the voltage plane (which can be reduced to 0V) and the clock signal (which can be uncoupled), the system achieves complete power elimination without requiring complex coordinated transitions, thereby reducing transition time and simplifying the overall control mechanism.
Solution Approach 2:
The patent introduces a voltage regulator as an intermediary component that enables smooth transition to 0V state. The voltage regulator acts as a mediator between the power supply and the processor core, allowing controlled voltage reduction to zero while maintaining system stability and enabling fast transitions without complex control logic in the processor itself.
3Ease of operation
If traditional ACPI C-states are used for power management, then compatibility and ease of operation are maintained, but power savings are limited with advanced manufacturing processes
Solution Approach 1:
The patent extends the existing ACPI C-state framework by introducing a new parameter state (C6/0V-state) that goes beyond the traditional C0-C5 states. This parameter change allows the voltage to be reduced to 0V and the clock to be uncoupled, enabling complete power elimination while maintaining compatibility with the existing ACPI control interface and ease of operation.
Data Source
AI summary
A system may comprise a plurality of processing units and a scheduler configured to maintain a record for each respective processing unit. Each respective record may comprise entries which may indicate 1) how long the respective processing unit has been residing in an idle state, 2) a present power-state in which the respective processing unit resides, and 3) whether the respective processing unit is a designated default (bootstrap) processing unit. The scheduler may select one or more of the plurality of processing units according to their respective records, and assign impending instructions to be executed on the selected one or more processing units. Where additional processing units are required, the scheduler may also insert an instruction to trigger an inter-processor interrupt to transition one or more processing units out of idle-state. The scheduler may then assign some impending instructions to these one or more processing units.