Secure Binding of CPU and Security Processor via Sideband Bus

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Solution Overview

Problem

Existing computing systems face vulnerabilities in data security due to the exposure of cryptographic keys in clear text, making them susceptible to attacks during cryptographic operations, especially when these keys are stored or transmitted outside the security processor.

Innovation Solution

A method is introduced to securely bind a CPU and a security processor using a shared wrapping key, ensuring that cryptographic keys are never stored in clear text outside the security processor, by generating and managing keys within the security processor and using a sideband bus for secure communication, thus preventing exposure to malware and ensuring the CPU and security processor are on the same platform.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If cryptographic keys are stored or transmitted in clear text for cryptographic operations, then operational convenience is improved, but security is worsened due to exposure to attacks

Engineering Contradiction:
Improveconvenience of cryptographic operationsVSAvoidsecurity of cryptographic keys
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent extracts the cryptographic key storage and management functions from the main CPU into a separate security processor. The CPU generates cryptographic keys and immediately transfers them to the security processor, which then manages all key operations. This separation ensures keys never reside in clear text in the CPU or main memory, eliminating the security vulnerability while maintaining operational convenience through the security processor's dedicated key management capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The security processor acts as an intermediary between the CPU and cryptographic operations. Instead of the CPU directly handling cryptographic keys in clear text, all key operations are mediated through the security processor, which receives keys from the CPU and performs encrypted operations. This intermediary layer prevents key exposure while enabling cryptographic functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If cryptographic keys are managed outside the security processor, then system flexibility is improved, but security is worsened due to potential malware exposure

Engineering Contradiction:
Improveflexibility of key managementVSAvoidexposure to malware attacks
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The system segments key management into two distinct components: key generation by the CPU and key storage/operation by the security processor. This segmentation allows the system to maintain flexibility in key generation while isolating the vulnerable key storage function in a secure, malware-proof environment. The security processor's isolated architecture prevents malware from accessing stored keys even if the main system is compromised.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary anti-action by pre-establishing a secure trust boundary around the security processor before any cryptographic operations occur. The security processor is designed with inherent security features that prevent malware injection and unauthorized access. By setting up this protective barrier in advance, the system neutralizes potential malware threats before they can compromise key security.

Inventive Principle:
Principle #9Preliminary anti-action

3Adaptability or versatility

If keys are transmitted between processors, then functional distribution is improved, but security is worsened due to transmission exposure

Engineering Contradiction:
Improvedistribution of cryptographic functionsVSAvoidsecurity during key transmission
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by establishing a secure communication channel between the CPU and security processor before any key transmission occurs. The sideband bus is configured with encryption and authentication mechanisms in advance. When keys need to be transmitted, the pre-established secure channel automatically protects the transmission, eliminating the need for additional security measures during the actual key transfer.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If a sideband bus is used for secure communication, then security is improved by preventing unauthorized access, but device complexity is worsened

Engineering Contradiction:
Improvesecurity of communication channelVSAvoidcomplexity of processor interconnection
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sideband bus serves as a dedicated intermediary communication channel between the CPU and security processor. Rather than using general-purpose buses that require complex security protocols, the sideband bus provides a purpose-built, inherently secure path for key-related communications. This specialized intermediary simplifies the overall system architecture by embedding security directly into the communication infrastructure rather than adding complex security layers to existing buses.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10877806B2Method and apparatus for securely binding a first processor to a second processor
Publication Date: 2020.12.29 INTEL CORP
  • US10877806B2 patent drawing
  • US10877806B2 patent drawing
  • US10877806B2 patent drawing

AI summary

In one embodiment, an apparatus comprises a first processor to generate a first cryptographic key in response to a request from a software application; receive a second cryptographic key generated by a second processor; encrypt the first cryptographic key using the second cryptographic key; and provide the encrypted first cryptographic key for use by the software application.