Identifying CPU Access to Shared Memory via Cache Coherency
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Solution Overview
Problem
In shared-memory multiprocessor systems, conventional memory access tracing methods cannot accurately identify which CPU is performing a memory access, as the necessary information is not available on the memory bus, requiring extensive monitoring of interconnects and mechanical effort, and local memory accesses are not visible on CPU interconnects.
Innovation Solution
A method that monitors memory access and cache coherency commands between computing devices, using information related to memory access and cache coherency commands to identify the CPU accessing shared memory by matching command histories and timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional memory access tracing is used by monitoring signals on the memory bus, then the tracing method is simple and does not require extensive monitoring, but the CPU making the access cannot be identified because the information used to identify which CPU is making the access does not flow on the memory bus
Solution Approach 1:
The patent uses cache coherency commands as an intermediary to bridge the gap between memory bus monitoring and CPU identification. By monitoring cache coherency commands that do flow on the memory bus and correlating them with memory access patterns, the system can identify the accessing CPU without directly monitoring interconnects between CPUs.
2Measurement precision
If a probe is connected to an interconnect between CPUs to monitor the flow of read/write packets, then the CPU making an access can be identified, but a significant amount of electronic and mechanical effort is required to monitor all interconnects between CPUs
Solution Approach 1:
The patent extracts the identification information from the cache coherency commands that are already present on the memory bus, rather than extracting it from multiple interconnects. This eliminates the need to monitor all CPU interconnects while still achieving accurate CPU identification through the use of coherency command analysis.
3Measurement precision
If only interconnect monitoring is performed, then some CPU access information can be obtained, but local memory accesses cannot be identified because local memory accesses do not appear on the interconnects between CPUs
Solution Approach 1:
The patent merges memory bus monitoring with cache coherency command monitoring to create a comprehensive tracing system. By combining these two monitoring approaches, the system can identify both local memory accesses (through memory bus monitoring) and remote accesses (through interconnect monitoring), eliminating the information loss that occurs with either method alone.
Data Source
AI summary
A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands.