CPU to Management Device Error Data Transfer via SMBus
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Solution Overview
Problem
Existing systems face challenges in efficiently transferring error data from a central processing unit (CPU) to a management device, particularly due to limitations in protocols and tools like EEPROM, which lack intelligent interaction for data storage and retrieval.
Innovation Solution
A method and system utilizing the SMBus protocol over an I2C bus to transfer error data, employing a time/date command and a data command to efficiently communicate failure information from machine check registers to an onboard management device, simplifying the communication protocol and enabling quick data reading and deciphering without additional overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If EEPROM is used to store error data, then data storage capability is improved, but intelligent interaction capability deteriorates
Solution Approach 1:
The patent combines EEPROM storage capability with CPU register interaction capability into a single bridge device. The bridge device includes an EEPROM interface connected to the I2C bus and a register interface connected to the CPU, merging the functions of simple storage (EEPROM) and intelligent interaction (CPU registers) into one integrated component that can both store error data and communicate with the CPU through standardized protocols.
Solution Approach 2:
The bridge device acts as an intermediary between the CPU and the EEPROM. It receives error data from CPU machine check registers through the I2C bus and stores it in the EEPROM, or retrieves it for system management. This intermediary resolves the contradiction by providing both the storage function of EEPROM and the intelligent interaction capability of CPU registers through a single mediating component.
2Reliability
If complex protocols are used for data transfer, then data transfer capability is improved, but communication efficiency deteriorates
Solution Approach 1:
The bridge device implements universal I2C bus interface that can communicate with both the CPU and the EEPROM using the same standardized protocol. This multi-functional interface handles multiple tasks (storing error data, retrieving error data, system management) through a single universal communication mechanism, eliminating the need for multiple specialized protocols and improving communication efficiency while maintaining reliable data transfer.
3Reliability
If additional overhead is added to communication protocol, then data transfer reliability is improved, but communication speed deteriorates
Solution Approach 1:
The patent extracts the communication overhead from the critical error data transfer path and places it in the non-critical system management path. The I2C bus handles error data collection with minimal overhead, while protocol verification and system management commands carry the necessary overhead. This separation allows fast error data collection without sacrificing reliability, as the overhead is handled in parallel through system management interfaces.
Data Source
AI summary
A mechanism is provided in a data processing system for transferring failure data from a processing unit to a management device. In response to detecting a failure of the processing unit, a computing device within the data processing system gathers failure information from machine check registers of the processing unit. The computing device generates a time stamp command communicating a time and date of the failure information and sends the time stamp command to the management device. The computing device generates at least one error data command communicating error data derived from the failure information and sends the at least one error data command to the management device.