CPU Socket Memory Expander BIOS Reconfiguration

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Solution Overview

Problem

The increasing number of CPU cores outpaces the growth of available memory and I/O circuitry, leading to performance limitations in virtualized applications due to insufficient memory, resulting in higher software licensing costs for customers.

Innovation Solution

Transforming a CPU socket into a memory and/or I/O expander by initializing multiple CPU sockets, where one core acts as a memory or I/O controller, allowing another core to access additional memory and I/O resources, effectively reporting the first core as having zero cores to reduce licensing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If customers purchase servers with more CPU sockets to increase system memory capacity, then memory capacity is improved, but software licensing costs increase

Engineering Contradiction:
Improvesystem memory capacityVSAvoidsoftware licensing costs
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent makes a CPU socket serve multiple functions: it can operate as a traditional processing socket or be transformed into a memory/I/O expander socket. The BIOS circuit detects the configuration and reconfigures the socket's electronic circuits accordingly, allowing the same physical socket to provide either processing power or memory capacity depending on system needs, thereby reducing the need for additional sockets and associated licensing costs

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the operational parameters of a CPU socket by transforming its electronic circuit configuration. The BIOS circuit modifies how the socket's memory controllers and I/O lanes are assigned and reported to the operating system, effectively changing the socket's function from processing to memory expansion without physical hardware changes, thus increasing memory capacity per licensed socket

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the number of CPU cores increases faster than memory and I/O circuitry, then processing capability is improved, but performance in virtualized applications is limited due to insufficient memory

Engineering Contradiction:
Improveprocessing capabilityVSAvoidperformance in virtualized applications
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent adds a new dimension to CPU socket functionality by introducing a transformable state. Instead of simply adding more sockets or memory, the system transforms existing socket resources into memory capacity, creating a new operational dimension where sockets can dynamically switch between processing and memory expansion roles, thereby balancing processing power with adequate memory resources for virtualized workloads

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9734103B2Systems and methods for transforming a central processing unit (CPU) socket into a memory and/or input/output (I/O) expander
Publication Date: 2017.08.15 DELL PROD LP
  • US9734103B2 patent drawing
  • US9734103B2 patent drawing
  • US9734103B2 patent drawing

AI summary

Systems and methods for transforming a Central Processing Unit (CPU) socket into a memory and/or Input/Output (I/O) expander. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a plurality of CPU sockets, each of the CPU sockets having one or more cores, and each of the one or more cores being associated with a respective one or more electronic circuits, the one or more electronic circuits including at least one of: a memory controller or an input/output (I/O) controller; and a Basic Input/Output System (BIOS) circuit coupled to the plurality of CPU sockets, the BIOS circuit having access to program instructions that, upon execution by the BIOS, cause the IHS to: initialize the plurality of CPU sockets; and report an electronic circuit associated to a first core of a first CPU socket as being instead associated with a second core of a second CPU socket.