CPU Synchronization via Register Comparison Logic
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Solution Overview
Problem
Modern CPUs are no longer deterministic due to multi-threading and caching techniques, leading to issues in synchronizing computation points in fault-tolerant failsafe computer systems, particularly in safety-critical applications like railway systems, where erroneous instructions can be generated by faulty components.
Innovation Solution
A system that includes a schedule module to communicate synchronization points to CPUs, with logical AND modules to verify memory addresses and generate a processor sync signal, ensuring that CPUs execute instructions in a synchronized manner to validate safety-critical operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-threading and caching techniques are used in modern CPUs, then processing speed and efficiency are improved, but deterministic execution and synchronization capability deteriorate
Solution Approach 1:
The system performs preliminary actions by having CPUs write their current instruction pointer values to registers before comparison. The schedule module pre-establishes synchronization points in the code, and CPUs are required to write their state to designated registers at these points before any further execution proceeds, ensuring deterministic synchronization despite multi-threading and caching
Solution Approach 2:
The system implements feedback through the schedule module that monitors instruction pointer registers and generates synchronization signals based on whether CPUs have reached expected synchronization points. This feedback mechanism detects deviations from deterministic execution and can trigger corrective actions or error handling
2Reliability
If instruction lockstepping is implemented, then synchronization and reliability are improved, but processing speed and adaptability deteriorate
Solution Approach 1:
The system dynamically adjusts the level of synchronization required based on the execution context. Rather than forcing strict lockstepping at all times, the system allows CPUs to execute independently until synchronization points are reached, then verifies alignment and resumes independent execution, providing dynamic balance between speed and reliability
Solution Approach 2:
The system implements periodic synchronization checks at predetermined points in the instruction stream rather than continuous lockstepping. CPUs execute independently between synchronization points, and the schedule module periodically verifies that both CPUs are at expected instruction pointers, maintaining reliability without constant speed limitation
3Reliability
If synchronization verification is performed at every instruction, then reliability is improved, but processing speed and system complexity deteriorate
Solution Approach 1:
The instruction stream is segmented into blocks with synchronization points at predetermined locations. Rather than verifying every single instruction, the system checks synchronization at segment boundaries where instruction pointer registers are compared, providing reliable verification without the overhead of per-instruction checking
Data Source
AI summary
A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first memory address to a first register in response to the first CPU reaching the synchronization point, and a second CPU that writes a second memory address to a second register in response to the second CPU reaching the synchronization point. The system further includes a first logical AND module that writes a first value to a third register based on the first and second memory addresses and a second logical AND module that writes a second value to a fourth register based on the first and second memory addresses. The system also includes a scheduler module that selectively generates a processor sync signal based on the first and second value.