CPU Task Scheduling for Dedicated Instruction Contention
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Solution Overview
Problem
Existing CPU scheduling technologies, such as Linux CFS Scheduler, fail to consider instruction contention between dedicated processes, leading to excessive core usage and wasteful power consumption.
Innovation Solution
A task scheduler device that includes a dedicated instruction ratio acquisition unit, intra-CPU calculator configuration information recording unit, core allocation determination unit, and core allocation unit to optimize core allocation based on instruction execution ratios and hardware configurations, minimizing contention and reducing core usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing CPU scheduling technologies (e.g., Linux CFS Scheduler) are used to allocate CPU times to every process, then fairness between processes is secured, but instruction contention between dedicated processes is not considered, leading to excessive core usage and wasteful power consumption
Solution Approach 1:
The patent changes the scheduling parameters from simple process-based time allocation to instruction-type-aware allocation. By introducing dedicated instruction ratios and intra-CPU calculator configuration information as new parameters, the system optimizes core allocation to reduce instruction contention while maintaining fairness, thereby reducing unnecessary core usage and power consumption
Solution Approach 2:
The patent segments the CPU instruction types into dedicated instructions (e.g., SIMD) and general-purpose instructions, and allocates cores based on the specific instruction types each process executes. This segmentation allows the system to consider instruction contention characteristics and allocate cores more efficiently, avoiding the wasteful activation of excessive cores
2Productivity
If the number of cores is increased to avoid instruction contention, then performance between dedicated instructions is secured, but the number of activated cores increases, leading to wasteful power consumption
Solution Approach 1:
The patent performs preliminary analysis of dedicated instruction ratios and intra-CPU calculator configurations before core allocation. By pre-acquiring instruction execution characteristics and calculator configuration information, the system can determine optimal core allocation in advance, avoiding the need to activate excessive cores and reducing power consumption while maintaining performance
Solution Approach 2:
The patent introduces feedback mechanisms where the system acquires dedicated instruction ratios and intra-CPU calculator configuration information, then uses this feedback to optimize core allocation. This closed-loop approach ensures that cores are allocated based on actual instruction contention characteristics, preventing both performance degradation and unnecessary power consumption
3Loss of energy
If core allocation is optimized based on dedicated instruction ratios and intra-CPU calculator configurations, then instruction contention is reduced and power is saved, but system complexity increases due to additional acquisition and determination units
Solution Approach 1:
The patent designs the core allocation determination unit to perform multiple functions: acquiring dedicated instruction ratios, analyzing intra-CPU calculator configurations, determining optimal core allocation, and managing the allocation process. By making this unit multi-functional, the patent reduces the need for separate dedicated components, thereby reducing system complexity while achieving power savings through optimized allocation
Data Source
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AI summary
A task scheduler device (100, 100A, 200, and 200A) includes each application dedicated instruction ratio acquisition unit (110) that acquires an execution ratio of a dedicated instruction specialized for specific calculation, of each application that operates on a server, an intra-CPU calculator configuration information recording unit (150) that records the number of intra-CPU calculators as the number of instructions executable at the same time, a core allocation determination unit (120) that determines a core allocation destination to a same physical core, using the execution ratio of the dedicated instruction and the number of intra-CPU calculators, and a core allocation unit (160) that allocates logical cores (21 and 22) in which each process is operable, based on an identifier of the process and an identifier of the logical core (21 and 22), regarding the core allocation destination determined by the core allocation determination unit (120).