Heterogeneous CPU Thread Scheduling for Frame Rate and Latency

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Solution Overview

Problem

Existing CPU scheduling algorithms fail to consider application-specific factors like frame rate and latency requirements, necessitating manual resource allocation adjustments, which is inefficient and affects power consumption and temperature management.

Innovation Solution

An electronic device with a CPU comprising multiple cores of varying computing power, equipped with a policy hint module that calculates thread requirements and sends messages to a scheduler for optimal core allocation based on thresholds and load conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If manual resource allocation adjustment is used, then adaptability to different applications is improved, but device complexity and operation difficulty increase

Engineering Contradiction:
Improveadaptability to different applicationsVSAvoidresource allocation complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system enables self-service by implementing an automated thread scheduling mechanism where the processor autonomously analyzes thread characteristics (frame rate requirements, latency constraints) and allocates cores accordingly. This eliminates the need for manual resource allocation adjustments while maintaining adaptability across different applications and platforms.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The invention applies parameter changes by dynamically adjusting scheduling parameters based on thread-specific attributes. The system evaluates parameters such as frame rate requirements and latency constraints to determine optimal core allocation, automatically adapting to different application requirements without manual intervention.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If high computing power cores are allocated to all threads, then processing speed is improved, but power consumption and temperature increase

Engineering Contradiction:
Improvethread processing speedVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system implements local quality by matching thread requirements with appropriate core capabilities. Instead of uniformly allocating high computing power cores to all threads, the scheduler analyzes each thread's specific needs (frame rate, latency) and assigns threads to cores with suitable computing power levels, ensuring optimal performance while minimizing energy consumption.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention applies partial action by allocating computing power resources proportionally to thread requirements. Threads with high frame rate and latency requirements receive high computing power core allocation, while threads with lower requirements are assigned to lower computing power cores, avoiding excessive resource allocation and reducing overall power consumption.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If automated thread scheduling is implemented, then resource allocation efficiency is improved, but system complexity increases

Engineering Contradiction:
Improveresource allocation efficiencyVSAvoidscheduling system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system applies preliminary action by pre-defining scheduling policies and thresholds for different thread types. The automated scheduler uses predetermined criteria (frame rate requirements, latency constraints) to make allocation decisions, which simplifies the real-time scheduling process while maintaining high resource allocation efficiency across diverse applications.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250383932A1Electronic device and method for scheduling threads
Publication Date: 2025.12.18 MEDIATEK INC
  • US20250383932A1 patent drawing
  • US20250383932A1 patent drawing
  • US20250383932A1 patent drawing

AI summary

An electronic device is provided. The electronic device includes a memory storing a program instruction and a central processing unit (CPU) with a first core and a second core. The computing power of the first core is higher than the computing power of the second core. The CPU is configured to read and execute the program instruction to implement a scheduler, a policy hint module, and an application. The CPU is further configured to calculate the required computing power of a thread of the application. When the required computing power of the thread is higher than a threshold, the policy hint module is configured to transmit a message to the scheduler, and the message indicates that the thread has to be allocated to the first core.