Tile-Level CPU Interconnect for Dependent Tile Read Handling

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Solution Overview

Problem

Existing central processing units (CPUs) face inefficiencies in accessing multimedia data stored in a tile format, leading to increased energy consumption and performance impacts due to duplicate memory access and decompression of cache lines.

Innovation Solution

Implementing a tile computation block to detect dependencies between tile read requests, a tile hazard block to store dependent nodes, and a tile level handler to output cache lines, along with a scheduler to manage dependencies and optimize memory access paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the CPU accesses multimedia data in tile format using conventional methods, then the data can be retrieved from main memory, but duplicate memory access occurs leading to increased energy consumption and performance degradation

Engineering Contradiction:

Improveenergy consumptionVSAvoidCPU access efficiency

Core Design Contradiction:

Loss of energyVSProductivity

Solution Approach 1:

The system performs preliminary classification of tile read requests into head nodes and dependent nodes before memory access. The tile computation block detects dependencies and categorizes requests in advance, allowing the system to prepare optimized access paths before actual memory operations occur, thereby preventing duplicate accesses and reducing energy consumption

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediary blocks (tile computation block, tile hazard block, tile level handler) between the CPU and main memory. These intermediaries detect, classify, and optimize tile read requests, identifying dependencies and preventing duplicate memory accesses before they occur, thus reducing energy consumption while improving access efficiency

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If the CPU processes tile-formatted multimedia data, then data access is enabled, but unnecessary memory access bandwidth is consumed due to duplicate reads

Engineering Contradiction:

Improvememory access bandwidthVSAvoiddata access throughput

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The tile computation block performs preliminary detection and classification of tile read requests into head nodes and dependent nodes before memory access. This advance preparation identifies which requests are duplicates, allowing the system to optimize bandwidth usage by preventing unnecessary memory accesses while maintaining data access throughput

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where the tile computation block continuously monitors incoming tile read requests, compares them against previously processed requests, and identifies dependencies. This feedback loop enables real-time optimization of memory access patterns, reducing bandwidth consumption while maintaining efficient data access

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS12566709B2Tile level interconnect design for central processing unit image access patterns

Publication Date: 2026.03.03 QUALCOMM INC

AI summary

Aspects of the disclosure are directed to providing access to multimedia data in a tile format. In accordance with one aspect, the disclosure includes detecting one or more dependencies of a first tile read request with a second tile read request by classifying a head node and a dependent node; sending the first tile read request to a main memory; storing the dependent node in a buffer; and outputting a first cache line and a second cache line using the first tile read request.