Multiprocessor Timer Synchronization via Offset Table Updates
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Solution Overview
Problem
In multi-processor systems with asynchronous clock sources, synchronizing processor timers is challenging due to potential drift between internal timers, leading to performance degradation and issues with timestamp accuracy, especially when external access is required frequently.
Innovation Solution
A method and apparatus for synchronizing central processing units (CPUs) involve a processor synchronization device that updates timer values by determining offset values from an offset table, writing corrected timer values to cache lines, and causing the selected CPU to update its timer, allowing for synchronization without a common clock source, thereby minimizing timer drift and performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single shared resource or external access is used for timestamping, then timestamp accuracy is improved, but system performance degrades due to bus traffic and bottlenecks
Solution Approach 1:
The patent divides the timestamping function into local processor components (local counters and timestamp units) rather than using a single shared external resource. Each processor maintains its own timestamp counter, eliminating the need for external bus access and removing the performance bottleneck while preserving timestamp accuracy through local operation.
2Productivity
If multiple processors use independent local counters, then system performance is improved by eliminating external access, but timer synchronization deteriorates due to drift between processors on different clock sources
Solution Approach 1:
The patent implements a feedback mechanism where the synchronization unit continuously monitors timer values from multiple processors and dynamically adjusts offset values stored in the offset table. This feedback loop compensates for drift between processors on different clock sources, maintaining synchronization while allowing each processor to operate independently with its own local counter.
Solution Approach 2:
The patent dynamically changes the offset parameter in the offset table based on measured drift between processors. By adjusting these offset values, the system compensates for timing differences between processors on different clock sources, maintaining synchronization without requiring a common clock source or sacrificing performance.
3Reliability
If system software synchronization is used, then timer synchronization is improved, but performance deteriorates due to the complexity of synchronization and the impact of large drift rates
Solution Approach 1:
The patent introduces a dedicated hardware synchronization unit as an intermediary between processors and the synchronization function. This specialized hardware component handles all synchronization operations, including monitoring timer values, calculating drift, and updating offset tables, thereby eliminating the need for complex software synchronization routines and their associated performance penalties.
Data Source
AI summary
Updating timers of central processing units (CPUs) in a multiprocessor apparatus involves the repeated performance of update operations by a device that is coupled to the CPUs via a memory interface. The operations include selecting one of the plurality of CPUs and determining an offset value that estimates a delay time to process a timer update at the selected CPU. A corrected timer value of the selected CPU is determined based on the offset value and a reference time. The corrected timer value is written to a cache line of the selected CPU to cause the selected CPU to update the timer of the selected CPU.