CPU Verification Mirror Model for Interrupt and State Divergence
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Solution Overview
Problem
Existing methods for verifying computer processor designs face challenges in simulating interrupts, handling volatile registers, and maintaining synchronization between reference models and processor designs, leading to inefficiencies and incomplete verification.
Innovation Solution
A computer-implemented method using an instruction accurate reference model (RM) with a mirror storage memory to maintain lock-step synchronization with the processor design under test (DUT), allowing for efficient comparison and verification, even in the presence of interrupts and volatile registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation of reference model is performed to verify processor design, then verification accuracy is improved, but simulation breaks down when interrupts are allowed in the design under test
Solution Approach 1:
The verification system is segmented into two independent simulation environments: a cycle-accurate reference model for handling interrupts and asynchronous events, and an instruction-accurate model for verifying instruction execution. This segmentation allows each component to specialize in specific verification aspects, preventing simulation breakdown when interrupts occur.
Solution Approach 2:
A control mechanism acts as an intermediary between the reference model and the design under test, coordinating their execution. The control steers both models through corresponding instructions and events, ensuring they remain synchronized despite different simulation approaches and interrupt handling mechanisms.
2Productivity
If instruction accurate reference model is used for verification, then verification speed is improved, but ability to handle asynchronous events and interrupts is worsened
Solution Approach 1:
The verification system separates concerns by using a cycle-accurate reference model specifically for handling interrupts and asynchronous events, while an instruction-accurate model handles instruction execution verification. This segmentation allows the instruction-accurate model to operate at high speed without being burdened by complex interrupt handling.
Solution Approach 2:
The control mechanism serves as an intermediary that coordinates between the two models, ensuring that when asynchronous events occur in the design under test, the reference model appropriately responds while maintaining synchronization with the instruction-accurate model's execution flow.
3Measurement precision
If direct comparison between DUT and RM data structures is performed, then verification accuracy is maintained, but access efficiency and comparison speed are worsened
Solution Approach 1:
The system creates a mirror copy of the reference model's data structures in a separate memory space. This mirror memory contains identical data structures that can be accessed and compared more efficiently, while the original reference model data structures remain intact for accurate verification reference.
4Reliability
If verification continues despite differences between DUT and RM, then verification completeness is improved, but risk of false verification results is worsened
Solution Approach 1:
The system dynamically adjusts its verification behavior based on the type of difference detected. When differences are found between DUT and RM, the system updates the mirror memory to reflect the DUT's state, allowing verification to continue. This dynamic adaptation enables comprehensive verification while maintaining accuracy by selectively updating reference data.
Data Source
AI summary
This document concerns using of an Instruction Accurate reference model of a hardware micro-architecture as the reference to verify a central processing unit (CPU) hardware implementation, include the following. 1) A ‘mirror’ mechanism that enables the VC to maintain an exact copy of the internal architectural state of the DUT. 2) A ‘volatile’ algorithm that allows the VC/RM to adapt its internal state when that state is not architecturally defined, but micro-architecturally (e.g. implementation) defined. 3) A use of ‘speculative execution’ to explore different possible permissible paths through the execution state space of the RM especially in response to asynchronous events and hidden details of the DUT implementations. 4) A technique described as ‘convergence’ which allows the RM to adapt its internal state after a divergence in behaviour/state between the DUT and RM, allowing the verification process to continue.