CPU Parallel Execution via Virtual Context Switching
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Solution Overview
Problem
Current CPU technologies face limitations in parallel performance due to their limited capability, which cannot be adequately addressed by increasing CPU hardware without significant overhead and cost, especially in big data processing scenarios where data requests are often homogeneous and lack correlation.
Innovation Solution
A method and apparatus that improve CPU parallel performance by acquiring and executing executable codes corresponding to the maximum degree of parallelism, utilizing pre-compiled code programs based on the maximum number of parallel threads provided by the CPU, allowing for efficient parallel processing without additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more CPU hardware is added to improve parallel performance, then parallel processing capability is improved, but hardware cost and complexity increase
Solution Approach 1:
The patent creates virtual copies of CPU execution contexts through thread contexts that can be rapidly switched. Instead of adding physical CPU cores, the system copies and manages multiple thread contexts (including saved register states, program counters, and stack pointers) that can be activated on existing cores, effectively creating virtual parallel processing capabilities through software-based context copying and switching mechanisms
Solution Approach 2:
The patent replaces the mechanical approach of adding physical CPU hardware with a software-based context switching mechanism. By using register stacks and context management data structures to store and restore CPU state, the system substitutes physical hardware expansion with software-controlled virtualization, allowing parallel thread execution on single or few physical cores without additional hardware overhead
2Productivity
If CPU hardware is upgraded to meet parallel requirements, then parallel performance is improved, but development cycle and cost increase
Solution Approach 1:
The patent performs preliminary actions by pre-allocating and organizing register stacks and context structures before parallel execution is needed. The system prepares multiple thread contexts with initialized register states and stacks in advance, so when parallel processing is required, the contexts are already ready for rapid switching without requiring hardware reconfiguration or lengthy setup procedures
Solution Approach 2:
The patent implements dynamic context switching that allows the system to adaptively allocate and switch between thread contexts based on runtime conditions. The context manager can dynamically select which thread context to activate on each CPU core, enabling flexible parallel execution patterns that can be adjusted without hardware changes, providing immediate responsiveness to varying parallel processing demands
3Productivity
If hyper-threading is added to improve parallel performance, then parallel capability is improved, but CPU hardware overhead increases
Solution Approach 1:
The patent makes existing CPU hardware resources universal by designing a context management system where the same physical registers, stacks, and execution units can serve multiple thread contexts sequentially. Instead of dedicating separate hardware resources to each thread (as in hyper-threading), the system allows one set of hardware resources to be universally shared across many virtual threads through rapid context switching, eliminating the need for duplicate hardware structures
Data Source
AI summary
Implementations of the present specification provide a method, an apparatus, and an electronic device for improving parallel performance of a CPU. The method includes: attempting to acquire data requests that are of a same type and that are allocated to the CPU core; determining a number of requests that are specified by the acquired one or more data requests; and in response to determining that the number of requests is greater than or equal to a maximum degree of parallelism: executing executable codes corresponding to the maximum degree of parallelism, wherein the maximum degree of parallelism is a maximum number of parallel threads executable by the CPU, and wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism at a time that is prior to a time of the executing.