3D Stacked Voltage Regulator Module for CPU Power Delivery
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Solution Overview
Problem
Current power delivery systems for CPUs, typically using a single supply voltage, lack the necessary area to route separate voltages to multiple CPU cores, cache, and I/O components, limiting power efficiency and preventing variable voltage supply to inactive or non-critical components.
Innovation Solution
A multi-Vcc voltage regulator module (VRM) die is bonded directly to the CPU die in a 3D packaging configuration, providing separate regulated voltage supplies to each component, reducing impedance and enabling efficient power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single supply voltage is used for multiple CPU cores, cache and I/O components, then the board area required is reduced, but power efficiency deteriorates because separate voltage control for individual components is lost
Solution Approach 1:
The patent segments the power delivery system by providing separate voltage regulators and voltage supply paths for different CPU components (cores, cache, I/O). Each component group receives independently controllable voltage, allowing selective power management and improved power efficiency without requiring excessive board area.
Solution Approach 2:
The patent transitions from a planar (2D) board-level power distribution to a three-dimensional (3D) package-level power delivery architecture. By stacking voltage regulators and power delivery networks in multiple layers within the CPU package, separate voltage paths are achieved without proportionally increasing board area.
2Use of energy by moving object
If separate supply voltages are routed to multiple CPU cores, cache and I/O components, then power efficiency is improved through variable voltage supply, but the board area and routing complexity increase
Solution Approach 1:
The patent moves power delivery from the board level (2D) to the package level (3D), stacking voltage regulators and power networks in multiple layers within the CPU package. This enables separate voltage routing to different components without requiring additional board area, as the power paths are established in the vertical dimension within the package.
Solution Approach 2:
The patent integrates multiple voltage regulators and power delivery networks into a unified package-level architecture that is coupled to the CPU die. This merging of power delivery functions within the package eliminates the need for extensive external routing while maintaining separate voltage control for different components.
3Ease of manufacture
If a remote motherboard VRM is used to supply power, then manufacturing is simplified, but impedance and response time delays increase due to longer power delivery paths
Solution Approach 1:
The patent combines the voltage regulators with the CPU package in an integrated architecture, eliminating the remote motherboard VRM configuration. This merging of power delivery functions into the package reduces the physical distance between power sources and load, thereby reducing impedance and response time delays while maintaining manufacturing feasibility through standardized package processes.
Solution Approach 2:
The patent introduces an intermediate power delivery network within the CPU package that acts as a mediator between the external power source and the CPU components. This intermediate network includes on-package voltage regulators and power distribution layers that reduce the effective impedance and delay by providing local voltage regulation closer to the load.
Data Source
AI summary
A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.