CPU Power Management via Watchdog Timer Anomaly Detection

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Solution Overview

Problem

Image forming apparatuses face challenges in efficiently transitioning between power-saving and normal operating modes, particularly when the second CPU enters an anomalous state, which can lead to unintended power-offs and data loss if not managed properly.

Innovation Solution

Incorporating a watchdog timer (WDT) and anomaly-detection circuitry that monitors the second CPU's state, triggering a reset and power supply control to ensure the first CPU remains powered on and ready for reboot, even during power-saving mode, to prevent data loss and ensure smooth transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the second CPU is used to monitor the network in power-saving mode, then power consumption is reduced, but the system reliability deteriorates when the second CPU enters an anomalous state

Engineering Contradiction:
Improvepower consumptionVSAvoidsystem reliability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent introduces a watchdog timer as an intermediary component that monitors the second CPU's operation. When the second CPU enters an anomalous state (fails to update the watchdog timer), the watchdog timer triggers a reset signal to restore normal operation, thereby maintaining system reliability while the second CPU continues to monitor the network in power-saving mode

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a feedback mechanism where the second CPU periodically updates a watchdog timer register to indicate normal operation. If the watchdog timer overflows (indicating the second CPU has entered an anomalous state), a reset signal is generated to feedback to the second CPU, causing it to restart and recover from the anomalous state

Inventive Principle:
Principle #23Feedback

2Loss of energy

If the first CPU is powered off in power-saving mode, then power consumption is reduced, but data loss occurs when an unexpected anomaly requires immediate processing

Engineering Contradiction:
Improvepower consumptionVSAvoiddata loss
Core Design Contradiction:
Loss of energyVSLoss of information

Solution Approach 1:

The patent introduces a watchdog timer as an intermediary monitoring system that independently tracks the operational state of the second CPU even when the first CPU is powered off. This allows the system to detect anomalies and trigger appropriate responses without requiring the first CPU to remain powered on, thus maintaining power savings while preventing data loss through timely anomaly detection and recovery

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9392133B2Information processing apparatus and image forming apparatus
Publication Date: 2016.07.12 FUJIFILM BUSINESS INNOVATION CORP
  • US9392133B2 patent drawing
  • US9392133B2 patent drawing
  • US9392133B2 patent drawing

AI summary

An information processing apparatus includes a first central processing unit, a second central processing unit, and a returning unit. The first central processing unit has a normal operating state and a power-saving state in which power consumption is lower than in the normal operating state. The second central processing unit causes the first central processing unit to return to the normal operating state from the power-saving state. The returning unit causes the first central processing unit to return to the normal operating state in a case where the second central processing unit enters an anomalous state after the first central processing unit has entered the power-saving state.