CPU+DPU Heterogeneous Architecture for Service Function Chain Parallelization

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Solution Overview

Problem

Traditional computing architectures based on CPU alone face bottlenecks in handling diversified scenarios and service requirements, leading to reduced forwarding performance and inefficient SFC deployment, as they struggle with increased network bandwidth and concurrent processing demands.

Innovation Solution

An efficient parallelization and deployment method for multi-objective service function chains (SFCs) is introduced using a CPU+DPU platform, which includes constructing a heterogeneous computing architecture, converting serial SFCs to parallel SFCs, deploying VNFs based on topological order, and employing a DPU processing strategy for real-time tasks, along with a deep reinforcement learning algorithm for adaptive deployment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional CPU-based computing architecture is used, then system simplicity is maintained, but forwarding performance deteriorates under increased network bandwidth and concurrent processing demands

Engineering Contradiction:
Improveforwarding performanceVSAvoidcomputing architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the computing architecture into two distinct parts: CPU for control plane operations and DPU for data plane operations. This segmentation allows each component to specialize in its strengths, with DPU handling high-speed packet forwarding and CPU managing complex service function chains, thereby resolving the contradiction between forwarding performance and architectural complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces DPU as an intermediary component between the network interface and the CPU. The DPU acts as a mediator that offloads packet processing tasks from the CPU, enabling high-speed forwarding while maintaining system manageability through centralized control by the CPU orchestrator.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If serial SFC deployment is used, then deployment simplicity is maintained, but processing efficiency deteriorates due to sequential execution of VNFs

Engineering Contradiction:
Improveprocessing efficiencyVSAvoiddeployment complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic SFC deployment by introducing parallel execution capabilities alongside traditional serial execution. The system can dynamically select between serial and parallel deployment modes based on service requirements, allowing VNFs to execute in parallel when independence conditions are met, thereby improving processing efficiency while maintaining deployment flexibility.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent segments the SFC deployment into independent VNF modules that can be executed separately in parallel. By identifying independence relationships between VNFs, the system divides the sequential chain into parallel segments, improving processing efficiency while maintaining manageable deployment complexity through modular design.

Inventive Principle:
Principle #1Segmentation

3Productivity

If DPU is introduced for high-speed forwarding, then forwarding performance is improved, but system complexity increases due to heterogeneous architecture management

Engineering Contradiction:
Improveforwarding performanceVSAvoidarchitecture management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a universal orchestrator that can manage both CPU and DPU resources through a unified interface. The orchestrator provides multi-functional capabilities including resource allocation, SFC deployment, and performance monitoring across heterogeneous components, thereby simplifying architecture management despite the introduction of DPU.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent incorporates feedback mechanisms where the orchestrator continuously monitors system state and dynamically adjusts resource allocation between CPU and DPU. This feedback loop enables adaptive management of the heterogeneous architecture, optimizing forwarding performance while maintaining manageable system complexity through real-time coordination.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11936758B1Efficient parallelization and deployment method of multi-objective service function chain based on CPU + DPU platform
Publication Date: 2024.03.19 NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
  • US11936758B1 patent drawing
  • US11936758B1 patent drawing
  • US11936758B1 patent drawing

AI summary

An efficient parallelization and deployment method of a multi-objective service function chain based on a CPU+DPU platform solves the problem of multi-objective deployment by constructing a heterogeneous computing architecture composed of an orchestrator and a server based on a CPU+DPU structure; the orchestrator is responsible for receiving an SFC request from a network operator; an SFC deployment algorithm based on deep reinforcement learning is operated, including a parallel strategy, a VNF topological order strategy and a DPU processing strategy to obtain an optimal deployment scheme of each request; then a resource management module is invoked to manage resources; and finally, a driver module is invoked to transmit the deployment scheme to a server for placement, and the server completes the deployment of SFC by using the CPU or the DPU respectively according to the deployment scheme.