CR Oscillator Resistor Network for High-Frequency Operation

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Solution Overview

Problem

The existing CR oscillator design requires high-voltage withstand capabilities for the first-stage inverter, leading to increased propagation delay and restricted oscillation frequency due to the need for high-voltage components.

Innovation Solution

The CR oscillator incorporates odd-number stages of logic inversion elements connected in series, with two or more resistors and a capacitor connected between the output nodes, where the intermediate node's electric potential is used to supply the input node of the first logic inversion unit, allowing for a resistance ratio adjustment to keep the input-node electric potential within the power-supply and ground limits, thus avoiding the need for high-voltage components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a high-voltage withstanding inverter is used for the first-stage inverter to handle instantaneous high voltage exceeding power supply voltage, then the inverter can withstand the high voltage, but the propagation delay time increases and oscillation frequency is reduced

Engineering Contradiction:
Improvehigh-voltage withstanding capabilityVSAvoidpropagation delay time
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent introduces a voltage clamping circuit as an intermediary component between the first-stage inverter and the rest of the oscillator circuit. This clamping circuit captures and dissipates the instantaneous high voltage spikes, preventing them from reaching the first-stage inverter. As a result, the inverter only needs to handle normal operating voltage levels, maintaining fast propagation delay while still protecting the circuit from voltage excursions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a high-voltage withstanding inverter is used for the first-stage inverter, then the inverter can withstand high voltages, but the oscillation frequency is restricted by the longer propagation delay time

Engineering Contradiction:
Improvehigh-voltage withstanding capabilityVSAvoidoscillation frequency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The voltage clamping circuit acts as a mediator that isolates the first-stage inverter from high-voltage stress. By clamping the voltage to safe levels, the inverter operates in its optimal frequency range with standard-speed components, thereby maximizing oscillation frequency while maintaining circuit reliability against voltage spikes.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the input voltage of the first-stage inverter instantaneously becomes a high voltage exceeding power supply voltage, then the inverter must be designed for high-voltage operation, but this increases device complexity and reduces performance

Engineering Contradiction:
Improvevoltage toleranceVSAvoidinverter design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Rather than designing complex high-voltage inverters, the patent uses a simple voltage clamping circuit as an intermediary protective layer. This approach maintains inverter design simplicity while providing robust voltage tolerance through the clamping mechanism, avoiding the need for complex high-voltage component design.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10560077B2CR oscillator
Publication Date: 2020.02.11 KIOXIA CORP
  • US10560077B2 patent drawing
  • US10560077B2 patent drawing
  • US10560077B2 patent drawing

AI summary

A CR oscillator has a first logic inversion unit including odd-number stages of logic inversion elements connected in series, a second logic inversion unit including odd-number stages of logic inversion elements connected in series, the second logic inversion unit being connected to a latter stage of the first logic inversion unit, and two or more resistors and a capacitor connected in series between an output node of the first logic inversion unit and an output node of the second logic inversion unit. An electric potential in accordance with an electric potential of an intermediate node between the two or more resistors is supplied to an input node of the first logic inversion unit.