CR-SAR ADC Preset Sampling for Extended Input Range
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Solution Overview
Problem
Conventional top-plate sampling charge redistribution successive approximation register (CR-SAR) analog to digital converters (ADCs) suffer from an attenuated input range due to parasitic capacitance, which negatively impacts the Signal to Noise-and-Distortion Ratio (SNDR) and effective number of bits (ENOB).
Innovation Solution
The ADCs are modified to preset the digital to analog converter (DAC) weights during the sampling phase, adding a digital offset that extends the input range by predicting the next input sample and adjusting the DAC control values, followed by a subtraction of the offset to achieve an accurate digital output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional top-plate sampling CR-SAR ADC is used, then the conversion process is simple, but the input range is attenuated due to parasitic capacitance
Solution Approach 1:
The patent applies preliminary action by presetting the DAC weights during the sampling phase before the actual conversion occurs. The controller predicts the next input sample and pre-adjusts the DAC control values to compensate for parasitic capacitance effects, thereby extending the input range without significantly increasing conversion complexity
Solution Approach 2:
The patent changes the DAC control values (digital weights) dynamically based on predicted input samples. By adjusting these parameters in advance during sampling and compensating after conversion, the system extends the effective input range while maintaining a relatively simple conversion process
2Device complexity
If conventional CR-SAR ADC is used, then the circuit structure is simple, but the SNDR is reduced due to parasitic capacitance effects
Solution Approach 1:
The patent implements feedback by using the predicted next input sample to adjust the DAC preset values. The controller continuously monitors and adjusts the DAC control values based on predicted inputs, creating a feedback mechanism that compensates for parasitic capacitance and improves SNDR while keeping the circuit structure relatively simple
Solution Approach 2:
By presetting the DAC weights in advance based on predicted input samples, the system proactively compensates for parasitic capacitance effects before they degrade the SNDR, thereby maintaining measurement precision without significantly complicating the circuit structure
3Ease of operation
If conventional ADC sampling is used, then the sampling process is straightforward, but the effective number of bits is reduced
Solution Approach 1:
The patent dynamically changes the DAC control values (digital weights) during sampling based on predicted input samples. This parameter adjustment extends the effective number of bits by compensating for parasitic capacitance effects while keeping the sampling process relatively straightforward
Solution Approach 2:
The controller performs preliminary adjustment of DAC weights during the sampling phase based on predicted inputs, thereby improving the effective number of bits without significantly complicating the sampling operation
Data Source
AI summary
An analog to digital converter including a digital to analog converter (DAC), a comparator, and a controller. The DAC includes a sample node and a capacitor array controlled by a digital control input. The comparator compares a voltage of the sample node with a reference voltage to generate a comparison value. The controller presets the digital control input, prompts the DAC to sample the input voltage onto the sample node, resets the digital control input, and performs a conversion by successively adjusting the digital control input based on the comparison value to determine a digital output. A preset value is subtracted from the digital output to provide an adjusted digital output. A sample predictor predicts the next sample to determine the preset value used to adjust the sample node within a full scale range after DAC reset.