Crack Arresting Cavities in 2.5D Substrates
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Solution Overview
Problem
Thin wafer handling in 2.5D and 3D technologies faces challenges due to wafer bow and cracking, as well as thermal issues leading to warpage and cracking of components during assembly, particularly in Chip-on-Wafer-on-Substrate (CoWoS) technologies.
Innovation Solution
The method involves etching crack arresting cavities in a substrate device with conductive vias, mounting chip devices, depositing an encapsulation layer, and planarizing to form separated packages, which helps in managing assembly by arresting crack propagation and enhancing thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If thin wafer handling is performed in 2.5D and 3D technologies, then device integration is achieved, but wafer bow and cracking occur causing assembly difficulty
Solution Approach 1:
The substrate is divided into multiple isolated cavities that segment the wafer structure. These cavities prevent crack propagation across the entire wafer by creating discrete isolation zones, thereby maintaining wafer integrity during assembly while enabling device integration.
Solution Approach 2:
Encapsulation material is deposited beforehand to fill the cavities and provide cushioning support to the thin wafer regions. This pre-cushioning prevents warpage and cracking during subsequent assembly processes by compensating for thermal and mechanical stresses before they occur.
2Power
If thermal management is implemented in 2.5D and 3D technologies, then device performance is improved, but thermal expansion causes warpage and cracking
Solution Approach 1:
The encapsulation material with different thermal expansion properties is selectively placed in specific cavity regions beneath the wafer. This local quality modification allows differential thermal expansion management, accommodating thermal stresses without causing overall warpage or cracking while maintaining device performance.
Solution Approach 2:
The encapsulation material acts as an intermediary layer between the substrate and the thin wafer. This intermediary absorbs and distributes thermal expansion stresses, preventing direct transmission of thermal shocks that would cause warpage and cracking, thereby preserving structural stability during thermal operation.
3Reliability
If crack propagation is prevented, then package reliability is improved, but additional processing steps are required
Solution Approach 1:
The cavities are etched and encapsulation material is deposited in advance, before wafer assembly and bonding. This preliminary action prepares the crack-arresting structure beforehand, so that during subsequent assembly processes, cracks are automatically contained without requiring additional real-time intervention or complex processing steps.
Solution Approach 2:
The encapsulation material automatically fills the etched cavities through conformal deposition, and the cavity structure inherently provides crack arrest functionality. This self-service mechanism eliminates the need for additional complex processing steps to implement crack prevention, as the structure performs the protective function automatically during assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes thin wafer handling concerns, prevents cracking and warpage, and allows for scalable assembly of large devices or interposer structures, improving the reliability of package assembly processes.
Implementation Method 1
depositing an encapsulation layer over the chip devices and filling the crack arrests cavities
Implementation Method 2
etching one or more crack arresting cavities in a first side of a substrate device to form crack arrests
Implementation Method 3
planarizing a second side to reveal the vias on the second side
Data Source
AI summary
A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.