Crack Propagation Guides for Low-Damage Semiconductor Dicing

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Solution Overview

Problem

Existing dicing techniques for semiconductor chips, such as those using lasers, often cause damage during the separation process, and there is a need for methods to minimize this damage while effectively separating semiconductor chips from a substrate.

Innovation Solution

A method involving the formation of alternating layers of different materials, with crack propagation guides and trenches, to guide and control the propagation of cracks during the dicing process, ensuring minimal damage to the semiconductor chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional laser dicing techniques are used to separate semiconductor chips from substrate, then chip separation can be achieved, but damage occurs to the semiconductor chip during the separation process

Engineering Contradiction:

Improvechip separation qualityVSAvoidchip damage

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent divides the substrate into multiple layers with alternating material compositions (first layer stack with first and second materials, second layer stack with third and fourth materials). Crack propagation guides are formed at specific interfaces between these layers to segment the crack path, confining cracks to predetermined routes that avoid damaging the chip regions while enabling effective separation of chips from the substrate.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different material layers are strategically positioned at different locations: the first layer stack is formed over the scribe lane region where cracks are intended to propagate, while the second layer stack is formed over the chip region to protect it. This local differentiation ensures that crack propagation is guided away from sensitive chip areas, minimizing damage during the dicing process.

Inventive Principle:

Principle #3Local quality

2Object-affected harmful factors

If crack propagation guides are formed to guide cracks vertically, then horizontal crack propagation is reduced and chip damage is minimized, but the manufacturing process complexity increases

Engineering Contradiction:

Improvechip damageVSAvoidmanufacturing process complexity

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

Crack propagation guides are formed in advance during the manufacturing process, before the actual dicing operation. These guides are created by forming trenches and filling them with specific materials at defined interfaces between layer stacks. By preparing these guided paths beforehand, the patent ensures that when dicing occurs, cracks naturally follow the predetermined vertical paths, reducing horizontal propagation and chip damage without requiring complex real-time control during separation.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12451394B2Methods of manufacturing semiconductor chip including crack propagation guide

Publication Date: 2025.10.21 SK HYNIX INC

AI summary

There may be presented a method of manufacturing a semiconductor chip. A first layer stack in which first material layers and second material layers are alternately stacked is formed over a semiconductor substrate including a chip region and a scribe lane region, and first crack propagation guides are formed on the first layer stack. A second layer stack is formed on the first layer stack and the first crack propagation guides, and second crack propagation guides are formed. A semiconductor chip is separated from the semiconductor substrate.