Crack Stop Structure High Modulus Layer Dicing Stress
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Solution Overview
Problem
The effectiveness of crack stop structures in semiconductor devices is reduced due to the brittleness of low-k dielectrics and increasing stress levels during chip dicing, particularly in advanced chip designs with larger sizes and organic laminate designs, leading to ineffective prevention of crack propagation from the dicing region into the active chip area.
Innovation Solution
An advanced crack stop structure is introduced, which includes a high modulus layer in addition to the conventional interconnect structure levels, using materials like SiC, Si3N4, or metallic layers such as W, Ta, and Ti, to enhance the structural integrity and prevent crack propagation during the dicing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional crack stop structures are used with low-k dielectrics, then manufacturing complexity is reduced, but crack prevention effectiveness deteriorates due to the brittleness of low-k dielectrics
Solution Approach 1:
The patent applies composite materials by combining low-k dielectric layers with high modulus material layers in the crack stop structure. The high modulus material layer (made of materials like silicon nitride, silicon carbide, or tungsten) is deposited over the low-k dielectric to provide mechanical strength and crack resistance, while the low-k dielectric maintains its electrical insulation properties. This composite structure resolves the contradiction by maintaining manufacturing simplicity while significantly improving crack prevention effectiveness.
Solution Approach 2:
The patent applies local quality by selectively placing high modulus material layers only in the crack stop peripheral region surrounding the active chip area, rather than throughout the entire chip structure. This localized application provides enhanced mechanical strength precisely where cracks occur during dicing, while leaving the active chip area with its original low-k dielectric structure intact, thus maintaining both ease of manufacture and crack prevention effectiveness.
2Area of moving object
If chip size is increased for advanced designs, then functional capability is improved, but stress during dicing increases leading to more cracks
Solution Approach 1:
The patent applies preliminary action by pre-depositing high modulus material layers in the crack stop structure before the dicing operation. These layers are prepared in advance during the manufacturing process to withstand the stresses that will occur during subsequent dicing operations. The high modulus material layer is deposited conformally over the low-k dielectric in the peripheral region, creating a pre-reinforced structure that proactively resists crack propagation during dicing, thereby allowing larger chip sizes without proportionally increasing dicing stress.
3Adaptability or versatility
If organic laminate design is used, then design flexibility is improved, but structural integrity during dicing deteriorates
Solution Approach 1:
The patent applies local quality by concentrating the high modulus material layer specifically in the crack stop peripheral region, where structural integrity is most needed during dicing. The organic laminate design can be freely implemented in the active chip area to maintain design flexibility, while the peripheral crack stop region receives enhanced mechanical reinforcement. This localized differentiation allows the chip to benefit from both organic laminate design flexibility and improved structural integrity where required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The incorporation of a high modulus layer in the crack stop structure significantly improves the structural toughness, effectively preventing crack propagation and ensuring the integrity of the semiconductor chip by withstanding the stresses induced during the dicing operation.
Implementation Method 1
a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level
Data Source
AI summary
An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level.